25G Ethernet Intel® Arria® 10 FPGA IP User Guide

ID 683639
Date 3/29/2021
Document Table of Contents TX RSFEC

If you turn on Enable RS-FEC in the 25G Ethernet Intel FPGA IP parameter editor, the IP core includes Reed-Solomon forward error correction (FEC) in both the receive and transmit datapaths.
The IP core implements Reed-Solomon FEC per Clause 108 of the IEEE Standard 802.3by. The Reed-Solomon FEC algorithm includes the following modules:
  • 64B/66B to 256B/257B Transcoding
  • 257:80 gearbox
  • High-Speed Reed-Solomon Encoder
  • 80:66 gearbox

You cannot turn on both Enable RS-FEC and Enable IEEE 1588 in the 25G Ethernet Intel FPGA IP parameter editor.

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