25G Ethernet Intel® Arria® 10 FPGA IP User Guide

ID 683639
Date 3/29/2021
Document Table of Contents

1.2. 25G Ethernet Intel FPGA IP Supported Features

The 25G Ethernet Intel FPGA IP is designed to the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and designed to the IEEE 802.3by 25Gb Ethernet specification, as well as the IEEE 802.3ba-2012 High Speed Ethernet Standard available on the IEEE website (www.ieee.org). The MAC provides RX cut-through frame processing to optimize latency. The IP supports the following features:

  • PHY features:
    • Soft PCS logic that interfaces seamlessly to Intel® Arria® 10 FPGA 25.78125 gigabits per second (Gbps) serial transceivers.
    • IEEE 802.3-2018 Ethernet Standard Clause 108 optional soft Reed-Solomon forward error correction (RS-FEC).
  • Frame structure control features:
    • Support for jumbo packets, defined as packets greater than 1500 bytes.
    • Receive (RX) CRC removal and pass-through control.
    • Transmit (TX) CRC generation and insertion.
    • RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
    • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
  • Frame monitoring and statistics:
    • RX CRC checking and error reporting.
    • RX malformed packet checking per IEEE specification.
    • Optional statistics counters.
    • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 46 support.
    • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
  • Flow control:
    • Standard IEEE 802.3 Clause 31 and Priority-Based IEEE 802.1Qbb flow control.
  • Precision Time Protocol support:
    • Optional support for the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol (1588 PTP). This feature supports PHY operating speed with a constant timestamp accuracy of ± 3 ns and a dynamic timestamp accuracy of ± 1 ns.
  • Debug and testability features:
    • Programmable serial PMA local loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
    • TX error insertion capability.
    • Optional access to Native PHY Debug Master Endpoint (NPDME) for serial link debugging or monitoring PHY signal integrity.
  • User system interfaces:
    • Avalon® memory-mapped management interface to access the IP control and status registers.
    • Avalon® streaming data path interface connects to client logic.
    • Configurable ready latency of 0 or 3 clock cycles for Avalon® streaming TX interface.
    • Hardware and software reset control.

For a detailed specification of the Ethernet protocol refer to the IEEE 802.3 Ethernet Standard.