Intel Agilex® 7 FPGA and SoC FPGA M-Series
M-Series devices are optimized for compute- and memory-intensive applications. Leveraging Intel 7 process technology, this series delivers over 2X better fabric performance per watt compared to competing 7 nm FPGAs1. This series builds upon I-Series device features offering an extensive memory hierarchy including integrated high-bandwidth memory (HBM) and high-efficiency interfaces to DDR5 memory with a hard memory Network-on-Chip (NoC) to maximize memory bandwidth.
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Intel Agilex® 7 FPGA and SoC FPGA M-Series
Enable Next-Gen Applications with a Data Superhighway
The amount of data being processed in edge, cloud, and telecommunications has been booming exponentially for years, and the emerging bottleneck is the ability to move more data to the right places. M-Series FPGA—with in-package HBM2e memory, support for LPDDR5, DDR5, and DDR4 memory—features a new hardened memory network-on-chip (NoC) to enhance transport layers with more performance, improved efficiency, and fewer FPGA resources required.
The Go-To Solution for Massive Memory Bandwidth
Greater than 1 TBps total memory bandwidth in the M-Series FPGA drives fast data movement for your next-gen data center applications.
High-End FPGA Key Features
High Compute Capability
Do the work of multiple FPGA in one. Up to 37 TFLOPs of FP16 performance2, up to 116 Gbps transceiver rates, and up to 3.9M logical elements (LE) deliver extreme density in an FPGA.
Greater Memory Bandwidth
A hardened memory NoC supports the industry’s highest memory bandwidth at over 1 TBps using HBM2e and DDR5.
Performance and Power Efficiency
Intel 7 process technology helps achieve over 2x higher fabric performance per watt vs. competing 7 nm FPGA.1
Support for High-Bandwidth and Coherent Attach to Intel Processors
Directly attach M-Series FPGA to Intel® Xeon® Scalable processors over the PCIe 5.0 bus or utilize the new Compute Express Link (CXL) protocol for exceptional I/O performance in moving compute workloads between CPU and FPGA. Design with confidence because the PCIe 5.0 solution is PCI-SIG compliant and the CXL IP is fully validated and interoperated with available HOST CPUs and other ecosystem products.
Implementing CXL Discrete Accelerators with Intel Agilex® 7 FPGAs
Intel Agilex® 7 FPGAs support CXL via R-Tile hard IP.
Target Use Cases and Verticals
Test and Measurement
5G/6G testers, arbitrary waveform generators, and GHz radio frequency measurements.
Wireless and Wireline
High data-rate transmission, optical transport networks (OTNs), and network functions virtualization (NFV).
Data Center
HPC, cloud, and cryptocurrency mining.
Public Sector
Aerospace, radar, and government analytics.
Get Started
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Additional Resources
Explore more content related to Intel® FPGA devices such as development boards, intellectual property, support and more.
Support Resources
Resource center for training, documentation, downloads, tools and support options.
Development Boards
Get started with our FPGA and accelerate your time-to-market with Intel-validated hardware and designs.
Intellectual Property
Shorten your design cycle with a broad portfolio of Intel-validated IP cores and reference designs.
FPGA Design Software
Explore Quartus Prime Software and our suite of productivity-enhancing tools to help you rapidly complete your hardware and software designs.
Contact Sales
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Where to Buy
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Product and Performance Information
See backup for workloads and configurations. Results may vary. For more complete information about performance and benchmark results, visit intel.com/benchmarks.
Each Intel® Agilex™ FPGA DSP block can perform two FP16 floating-point operations (FLOPs) per clock cycle. Total FLOPs for FP16 configuration is derived by multiplying 2x the maximum number of DSP blocks to be offered in a single Intel® Agilex™ FPGA by the maximum clock frequency that will be specified for that block.