MIPI DSI-2 IP User Guide

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ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

3.2.1.2. Video Timing Tab Options

On the Video Timing tab, specify the parameters to set the timing of the video on the MIPI D-PHY interface.

Figure 8. Video Timing Tab Parameters
Table 11.  Video Timing Tab Parameter Description
Parameter Values Description
Video timing configuration values Manual This option selects the video timing configuration in operation. The IP currently only supports manual mode where all timing parameters are manually configured.
Validate video timing parameters On/Off When enabled, the video timing parameters are checked to ensure that they meet the configuration requirements (Refer to Configuration Requirements). If this is disabled, the checks are not performed and the IP is not guaranteed to function correctly.
Default value for HTOTAL 0–65536 Total horizontal line length in pixels, including active and blanking regions.
Default value for VTOTAL 0–65536 Total vertical picture size in video lines, including active and blanking regions.
Default value for HB_END 0–65536 Horizontal blanking period in pixels. The difference between HTOTAL and this value must equal the horizontal active line length in pixels. When the YCbCr 12bit data type is used, the difference must be equal to half of the horizontal active line length.
Default value for V1B_START 0–65536 Line number of first line of vertical blanking.
Important: This value must be set to zero.
Default value for V1B_END 0–65536 Line number of first line of active region. The interval between V1B_END and VTOTAL must be equal to the number of active lines per video frame.
Default value for HS_START 0–65536 Horizontal position of the start of horizontal sync pulse. This must be within the horizontal blanking region, HB_END.
Default value for HS_END 0–65536 Horizontal position of the end of horizontal sync pulse. This value must be between HS_START and HB_END.
Default value for V1S_VSTART 0–65536 Vertical position of the start of the vertical sync pulse. This value must be after V1B_START and before V1B_END.
Default value for V1S_HSTART 0–65536 Horizontal position of the start of the vertical sync pulse. This value must be within the horizontal blanking region (less than HB_END).
Default value for V1S_VEND 0–65536 Vertical position of the end of the vertical sync pulse. This value must be after V1S_VSTART and before V1B_END.
Default value for V1S_HEND 0–65536 Horizontal position of the end of the vertical sync pulse. This value must be between V1S_HSTART and HB_END.

Section Content
Configuration Requirements
Timing Calculation Examples

Level Two Title