MIPI DSI-2 IP User Guide

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ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples Example 1 Example 2
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

3.2.1.2.2. Timing Calculation Examples

The following are examples of how the video parameters are calculated:

Example 1

Table 12.  Settings Examples for Timing Parameters
Parameter Settings
MIPI data rate 2500 Mbps
MIPI lanes 1
DSI-2 data types YCbCr-20bit Loose (24 bits per pixel)
Video interface pixels in parallel 2
Active video dimensions 1280 pixels × 800 lines
Frame rate 90 Hz
Vertical front porch (VFP) 5 lines (e.g. panel recommendation)
Vertical back porch (VBP) 5 lines (e.g. panel recommendation)
Vertical sync active (VSA) 5 lines (e.g. panel recommendation)
Common video + MIPI clocks Disabled
Video clock rate 250 MHz
  1. Calculate the vertical parameters. If VFP, VSA, and VBP values are not specified by the panel manufacturer, these values can typically be a small value between 2 and 30.
    Parameter Calculation Value
    V1B_START Fixed 0
    V1S_VSTART VFP 5
    V1S_VEND VFP + VSA = 5+5 = 10
    V1B_END VFP + VSA + VBP = 5+5+5 = 15
    VTOTAL V1B_END + VACTIVE = 15+800 = 815
  2. Perform sanity checks to ensure the link is able to support the required bandwidth.
    The MIPI output channel has around 11% additional bandwidth, which is likely to be sufficient to support the MIPI signaling overheads.
  3. Calculate the horizontal total line length.
  4. Check that the calculated HTOTAL complies with HTOTALmin.
    As the calculated HTOTAL, 6816.6, is greater than the minimum, 4611, this complies with the minimum. However, all the horizontal parameters must be an integer multiple of the video input pixels in parallel, in this case 2. Therefore, the number must be rounded to the nearest multiple of pixels in parallel, i.e. 6816.
  5. Calculate the other horizontal parameters. Horizontal sync positions are often flexible and can be spread evenly within the blanking period between pixels 0 and HB_END. If these are specified by the panel manufacturer, take this information into consideration.If the video input is configured with multiple pixels in parallel, the horizontal sync positions (HS_START, HS_END, V1S_HSTART, V1S_HEND) should be multiplied by the number of pixels in parallel.
    Parameter Calculation Value
    HB_END HTOTAL-HACTIVE = 6816-1280 = 5536
    HS_START 0< HS_START< HB_END e.g. 200
    HS_END HS_START < HS_END < HB_END e.g. 400
    V1S_HSTART Align with HS_START 200
    V1S_HEND Align with HS_START 200
    HTOTAL As calculated above 6816

Example 2

Table 13.  Settings Examples for Timing Parameters
Parameter Settings
MIPI data rate 900 Mbps
MIPI lanes 4
DSI-2 data types RGB888 (24 bits per pixel)
Video interface pixels in parallel 2
Active video dimensions 1920 pixels × 1080 lines
Frame rate 60 Hz
Vertical front porch (VFP) 10 lines (e.g. panel recommendation)
Vertical back porch (VBP) 10 lines (e.g. panel recommendation)
Vertical sync active (VSA) 5 lines (e.g. panel recommendation)
Common video + MIPI clocks Enabled
  1. Calculate the vertical parameters. If VFP, VSA, and VBP values are not specified by the panel manufacturer, these values can typically be a small value between 2 and 30.
    Parameter Calculation Value
    V1B_START Fixed 0
    V1S_VSTART VFP 10
    V1S_VEND VFP + VSA = 10+5 = 15
    V1B_END VFP + VSA + VBP = 10+5+10 = 25
    VTOTAL V1B_END + VACTIVE = 25+1080 = 1105
  2. Perform sanity checks to ensure the link is able to support the required bandwidth.
    The MIPI output channel has around 18% additional bandwidth, which is likely to be sufficient to support the MIPI signaling overheads.
  3. Calculate the horizontal total line length. As the common video and MIPI clock are enabled, the video AXI4-Stream clock is the same rate as the MIPI PPI interface:
  4. Check that the calculated HTOTAL complies with HTOTALmin.
    As the calculated HTOTAL 3394 is greater than the minimum 3124, this is a valid configuration.
  5. Calculate the other horizontal parameters. Horizontal sync positions are often flexible and can be spread evenly within the blanking period between pixels 0 and HB_END. If these are specified by the panel manufacturer, take this information into consideration. If the video input is configured with multiple pixels in parallel, the horizontal sync positions (HS_START, HS_END, V1S_HSTART, V1S_HEND) should be multiplied by the number of pixels in parallel to convert from clock cycles to pixels.
    Parameter Calculation Value
    HB_END HTOTAL-HACTIVE = 3124-1920 = 1204
    HS_START 0< HS_START< HB_END e.g. 200
    HS_END HS_START < HS_END < HB_END e.g. 400
    V1S_HSTART Align with HS_START 200
    V1S_HEND Align with HS_START 200
    HTOTAL As calculated above 3394
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