MIPI DSI-2 IP User Guide

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ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

7. Appendix A: Functional Description

The MIPI DSI-2 TX IP receives video from the Altera Streaming Video Protocol (full variant). The Clocked Video Output (CVO) module from the Altera Video & Vision Processing (VVP) IP suite forms a video raster using the configured timing and inserts the incoming video into this raster. The Altera Streaming Video Protocol (full raster) format is used to carry the video from the CVO into the MIPI DSI-2 core.

The MIPI DSI-2 IP processes the video data and video synchronization information, then converts them into packets as defined by the MIPI DSI/DSI-2 specification to prepare them for transmission via the Altera MIPI D-PHY IP.

The Timing Monitor and Timing Control modules are only included when fixed latency mode is enabled. This mode records the timing of the video and synchronization pulses on arrival from the CVO. The MIPI DSI-2 packets are retimed using this information to ensure maximum timing accuracy with minimal additional FPGA resources consumption. When this mode is disabled, the MIPI DSI-2 IP operates on a minimum latency basis and there may be some variation in inter-packet timing on the MIPI external interface. For example, sync timing may be offset horizontally relative to the video.

The Timing Monitor records timestamps from the video and synchronization pulses from the CVO for use in controlling packet playout in Timing Control.

The MIPI DSI-2 Packetizer packs the input pixels to MIPI DSI-2 packet payload data as defined in the MIPI DSI-2 specification. Packet headers and checksums are attached. Syncs are converted into MIPI DSI-2 synchronization packets. When ECC and CRC calculation is enabled, these are inserted into the relevant part of the packets. When disabled, these values are fixed to zero.

A Packet Buffer holds the MIPI DSI-2 packets. When fixed latency mode is disabled, the packet buffer stores the packet data until a complete packet is ready to send, to ensure contiguous packets are sent on the MIPI D-PHY interface. In fixed latency mode, this is ensured by the fixed latency timing logic in Timing Control.

Timing Control holds packets until a fixed period from the corresponding events at the Timing Monitor has expired before allowing each packet to be forwarded to ensure fixed latency through the packetizer and packet buffer.

The Lane Distributor spreads the packet data across the configured number of lanes, as defined by the MIPI DSI-2 specification.

The PPI Interfacing module handles the signaling of the data to the MIPI D-PHY IP via the MIPI PHY-Protocol Interface (PPI) defined in the MIPI D-PHY specification.

An optional Avalon® memory-mapped control interface is presented, which allows access to the registers in both the MIPI DSI-2 core and CVO modules. The registers in the MIPI DSI-2 core only display the status information, while the registers in the CVO and Video Timing Generator allow for reconfiguration of the output video timing. When the control interface is disabled, the video timing is fixed according to the configuration in the Parameter Editor.

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