MIPI DSI-2 IP User Guide

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ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

3.2.1.1. IP Tab Options

On the IP tab, specify the parameters to configure the MIPI and video interface for your IP.

Figure 7. IP Tab Parameters
Table 10.  IP Tab Parameter Description
Parameter Range Selection Default Setting Description
Pixels in parallel 1, 2, 4 2 Select the number of pixels presented on each beat of the input video interface.
Pixels per video line 1–8192 128 Indicate the number of pixels on a video line. This must be set to the exact line length to be transmitted.
Use common clock for video input and MIPI output On/Off On When the common clock is enabled, the video input must be driven from the MIPI link clock for this interface. This allows the MIPI DSI-2 IP to operate with a single clock domain and enables the fixed latency mode option.
AXI4-S TDATA width 1–96 N/A This parameter indicates the calculated width of the video TDATA input based on the IP configuration. This value is fixed and cannot be changed.
MIPI DSI-2 data type
  • RGB 36bit
  • RGB_30bit
  • RGB 24bit
  • RGB 18bit (Packed)
  • RGB 18bit (Loose)
  • RGB 16bit
  • YCbCr 24bit
  • YCbCr 20bit (Packed)
  • YCbCr 20bit (Loose)
  • YCbCr 16bit
  • YCbCr 12bit
 RGB 24bit Select the MIPI DSI-2 data type to be used when video data is packed into MIPI DSI-2 packets. The pixel data received on the AXI4-Stream interface must correspond to this data type.
Number of lanes 1, 2, 4 2 MIPI lanes on the external MIPI D-PHY interface. This must correspond to the MIPI D-PHY IP configuration.
PPI bus width 2 2 This indicates the number of bytes per lane on the data interface on the PPI. This value is fixed and cannot be changed.
Direction Tx Tx This option is fixed to TX. The IP is currently only available as a transmitter.
Control and Status Registers (CSRs) On/Off On When Control and Status Registers are off, the control and status register interface is not included. Disabling this option reduces the IP resource utilization but the CVO and Video Timing Generator cannot be dynamically reconfigured.
CRC insertion On/Off On Cyclic redundancy check (CRC) processing. When CRC insertion is disabled, the IP does not calculate long packet payload CRC and it sets the fixed value zero in the checksum field. Disabling this parameter reduces the resource utilization in your system architecture where it is not required.
Note: If you choose to disable CRC insertion for your system, the output from the IP will not comply with the MIPI DSI-2 specification.
ECC insertion On/Off On Error correction code (ECC) processing. When ECC insertion is disabled, the IP does not calculate the header ECC code and sets the fixed value zero in the ECC field in all packet headers. Disabling this parameter reduces the resource utilization in your system architecture where it is not required.
Note: If you choose to disable ECC insertion for your system, the output from the IP will not comply with the MIPI DSI-2 specification.
Fixed latency mode On/Off On The fixed latency mode adheres strictly to the video timing configured in the IP. When disabled, the video is passed with minimum latency. So, the MIPI output follows the line and frame intervals configured. The sync locations may vary slightly within lines, depending on the timing configured. Enabling this option slightly increases logic and memory utilisation.
Note: Only use this option when common video input and MIPI clocks are enabled.
Buffer depth 128– 65536 4096 Configure the internal data buffer depth. This must be enough to hold at least 1.2 video lines. If the incoming video data is very bursty, increasing this option enhances resilience to data underflow errors within the IP. To assist you in selecting the appropriate buffer size, the currently selected buffer depth is translated into video lines and displayed by the IP. It also can be calculated using this formula:
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