MIPI DSI-2 IP User Guide

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ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

3.2.1.2.1. Configuration Requirements

Configuration of the video timing requires a detailed understanding of the requirements of the intended display in your system and Altera recommends that you consult your display manufacturer for guidance. When entering the horizontal timing parameters, it is important to calculate the values based on the video input clock rate. This clock rate may be different from the datasheet values.

You must consider the following factors described in this section when determining the timing configuration to ensure that the system is viable. Otherwise, the output video may be corrupted or lose synchronization. In some cases, it may be necessary to increase the MIPI data rate or increase the lane count on the MIPI D-PHY interface to ensure that sufficient bandwidth is available to carry the required video stream.

Figure 9. Video Timing Parameters

The timing parameters are defined in the same way as the Video Timing Generator IP in the Altera Video and Vision Processing Suite. Note that all horizontal values are defined in horizontal units rather than clock cycles. In the YCbCr 12-bit format, the horizontal unit is a pair of pixels, due to the way that 4:2:0 data is carried. In all other formats, the horizontal unit is a single pixel.

For example, if the IP is configured with 2 pixels-in-parallel on the AXI4-Stream video interface with the data type RGB 24-bit and HTOTAL=2200, then the line interval is 1100 clock cycles. This should be considered when calculating line intervals and frame rates.

Important:

The configuration of all horizontal timing parameters (HTOTAL, HB_END, HS_START, HS_END, V1S_HSTART, V1S_HEND) must be an integer value that is the multiple of the configured number of pixels in parallel at the input. For example, if the IP is configured with 2 pixels in parallel, then both HB_END and HTOTAL must be a multiple of 2.

Also, the relationship between HB_END and HTOTAL must always be:

For YCbCr 12-bit format, the relationship is:

Altera recommends that you calculate and observe the minimum value of HTOTAL that is supported for a given system. The following formula indicates the shortest line interval that is supported by the selected configuration of the IP.

If the MIPI D-PHY IP link is configured longer than the default timing interval parameters, this value requires a corresponding increase. This value is calculated and displayed in the Parameter Editor. If your HTOTAL value does not comply with this value, an error is displayed. Disabling the video timing parameter validation option avoids this error but may result in video corruption and loss of synchronization.

Note:
  • packed_pixel_width is the number of bits required to insert a single pixel into the packed output stream. For example, 16 for the RGB-16bit data type. When loosely-packed data types are selected, the packed pixel width should account for the additional bits consumed in these formats. For example, YCbCr 20bit (Loose) requires 24-bits per pixel when packing the video stream with unused bits, therefore the pixel width used in these calculations must use the higher value.
  • active_line_length is the number of pixels per video line.
  • lanes is the number of MIPI lanes configured in the MIPI DSI-2 IP and MIPI D-PHY IP.
  • ppi_width is the bit width of the PPI interface between the MIPI DSI-2 IP and MIPI D-PHY IP, which is fixed to 16.
  • pixels_in_parallel is the configured pixels in parallel at the streaming video input to the MIPI DSI-2 IP.

The line interval and frame rate can be calculated from the configured timing values. The video timing generation operates on the same clock used on the AXI4-Stream video input interface. When the option for the common video input and MIPI link clocks is enabled, this clock is the MIPI D-PHY link word clock, and this clock frequency is calculated and displayed in the MIPI D-PHY IP parameter editor for the configured IP. When the option for the common clocks is disabled, this is the frequency of your supplied input clock.

Refactoring this formula, if your frame rate and total line count is fixed, you can calculate the required horizontal timing parameters based on these values using the following formula. Note, you must ensure that HTOTAL complies with HTOTALmin:

It is important to consider the available bandwidth on both the AXI4-Stream and MIPI interfaces to ensure that your chosen video timing is feasible. The MIPI interface must have sufficient bandwidth to pass a line of video data within the line interval shown by the calculation above. An approximation of the configured peak data transfer rates on input and output can be calculated as follows:

For example, a system carrying YCbCr 20bit (Packed) data with a line length of 1280 pixels, 815 total lines per frame (active + blanking) at 60 frames per second has a peak input data rate of 1.25Gbps + MIPI signaling overheads.

When comparing input and output rates, the MIPI DSI-2 in-band sync signaling and MIPI D-PHY LP/HS transition duration must be taken into consideration. The above calculation for data_rate_output_bps ignores these values. The HTOTALmin calculation provides a more accurate horizontal timing estimate.

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