4.3.2. Video Input Clock
The Altera Streaming Video input interface axi4s_vid_in operates on the clk clock domain.
In MIPI DSI-2 IP version 1.0.0, the clk clock input must be connected to the LINK<x>_link_core_clk on the MIPI D-PHY IP. In this configuration, the IP processes the incoming video and produces the MIPI output using a single clock domain throughout and without any clock domain crossings. This results in deterministic processing latency especially with fixed latency mode enabled and reduced resource utilization.
In this configuration, the video source to the IP must also be running on the MIPI link clock. In systems where the video is generated in another domain, it can be transferred onto this domain before connecting to the MIPI DSI-2 IP using the Video Streaming FIFO IP in dual clock configuration. The synthesis design example exports the link clock as link_core_clk_bridge_out_clk and associated reset, which the user logic should use to drive the video into the MIPI DSI-2 video input.
From MIPI DSI-2 IP version 2.0.0 onwards, an additional user parameter CLOCKS_ARE_SAME allows the user to select whether the clk clock input is common with the MIPI PPI output clock or is independent.
When the CLOCKS_ARE_SAME parameter is enabled, the clock architecture is the same as that in version 1.0.0. When the parameter is disabled, the input clock is independent of the MIPI PPI and can be driven by any suitable clock. This allows a simpler system clock architecture with freedom to run the whole video pipeline in the FPGA on a single clock domain. When the input clock is independent, it is important to ensure that the clock provides video data at the input to the MIPI DSI-2 IP fast enough to ensure that the MIPI output is always satisfied and cannot underflow.
The AXI clock may operate at any frequency up to the maximum clock rate supported by the FPGA.