GTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 849710
Date 4/18/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application 5. Designing with the IP Core 6. Designing the IP Solution 7. Sharing Clocking and Applying SDC Constraints 8. Runtime Flow 9. Simulating the IP 10. Validating the IP 11. Appendix A: Functional Description 12. Registers 13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide
1. Overview x
1.1. About the GTS Dynamic Reconfiguration Controller IP 1.2. About the Document 1.3. Key Concepts 1.4. System Level Block Diagram 1.5. Design Checklist 1.6. IP Design Flow 1.7. Dynamic Reconfiguration 1.8. Design Considerations 1.9. Design Migration Guidelines 1.10. Design Flow Requirements
1.1. About the GTS Dynamic Reconfiguration Controller IP x
1.1.1. Release Information 1.1.2. Features 1.1.3. High-Level Functional Overview 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Terminology 1.2.4. Acronyms 1.2.5. Reference Documents and Training 1.2.6. GTS Dynamic Reconfiguration Target Applications
2. Quick Start Guide x
2.1. Steps to Generate and Run the Design Example 2.2. Steps to Create a Custom Dynamic Reconfiguration Design
2.1. Steps to Generate and Run the Design Example x
2.1.1. Generating the Design Example 2.1.2. Compiling the Design Example 2.1.3. Simulating the Design Example 2.1.4. Validating the Design Example
2.2. Steps to Create a Custom Dynamic Reconfiguration Design x
2.2.1. Simulating the Custom Design 2.2.2. Validating the Custom Design
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles 3.3. Generating HDL for Synthesis and Simulation 3.4. Using the Dynamic Reconfiguration Assignment Editor 3.5. Generating HSSI Dynamic Reconfiguration IP 3.6. Generating the Design Example 3.7. Compiling the Design Example
3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles x
3.2.1. Configuring the IP
3.2.1. Configuring the IP x
3.2.1.1. Configuring the IP Presets 3.2.1.2. Configuring the IP Parameters
3.4. Using the Dynamic Reconfiguration Assignment Editor x
3.4.1. Quartus User Flow
3.4.1. Quartus User Flow x
3.4.1.1. IP List 3.4.1.2. Dynamic Reconfiguration Group List 3.4.1.3. Properties 3.4.1.4. DR Group Visualization Pane 3.4.1.5. Messages Pane
3.6. Generating the Design Example x
3.6.1. Generated Directory Structure and Files
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Implementing Required AVMM Interface 4.6. Control and Status Interface 4.7. Implementing Mux Selector Interface 4.8. Implementing SRC Interface 4.9. Implementing Local AVMM Interface 4.10. Connecting the Interfaces 4.11. Signal Functions 4.12. Integrating the IP With User Logic 4.13. Integrating the IP With Your Board 4.14. Integrating the IP on the Stack With a Software Driver
5. Designing with the IP Core x
5.1. Release Constraints 5.2. DR Design Guidelines
6. Designing the IP Solution x
6.1. Dynamic Reconfiguration QSF Settings 6.2. Defining DR Combinations 6.3. Instantiating the Generated DR Group 6.4. Generating and Instantiating the DR Controller
9. Simulating the IP x
9.1. Design Example Features 9.2. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
9.2. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench x
9.2.1. Simulating the Design Example
9.2.1. Simulating the Design Example x
9.2.1.1. Simulating the Testbench Flow 9.2.1.2. Verifying the Simulation Results
10. Validating the IP x
10.1. List of Switches on the Developer Kit 10.2. Testing the Hardware Design Example 10.3. Troubleshooting and Debugging Issues
10.2. Testing the Hardware Design Example x
10.2.1. Configure the Clocks in Hardware 10.2.2. Program the FPGA 10.2.3. Running the Hardware Test
11. Appendix A: Functional Description x
11.1. AVMM Clock Crossing Bridge 11.2. AVMM Decoder 11.3. Mux Sel, Local AVMM, and SRC Interface 11.4. Dynamic Reconfiguration CSR
12. Registers x
12.1. Configuration Registers 12.2. GTS Transceiver PHY Registers
12.1. Configuration Registers x
12.1.1. Register Next ID Configuration 0 12.1.2. Register Next ID Configuration 1 12.1.3. Register Next ID Configuration 2 12.1.4. Register Next ID Configuration 3 12.1.5. Register Next ID Configuration 4 12.1.6. Register Next ID Configuration 5 12.1.7. Register Next ID Configuration 6 12.1.8. Register Next ID Configuration 7 12.1.9. Register Next ID Configuration 8 12.1.10. Register Next ID Configuration 9 12.1.11. Register Next ID Configuration 10 12.1.12. Register Next ID Configuration 11 12.1.13. Register Next ID Configuration 12 12.1.14. Register Next ID Configuration 13 12.1.15. Register Next ID Configuration 14 12.1.16. Register Next ID Configuration 15 12.1.17. Register Next ID Configuration 16 12.1.18. Register Next ID Configuration 17 12.1.19. Register Next ID Configuration 18 12.1.20. Register Next ID Configuration 19 12.1.21. Register Trigger 12.1.22. Register Trigger Status 12.1.23. Register Error Configuration 12.1.24. Register Error Status
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application
5. Designing with the IP Core
6. Designing the IP Solution
7. Sharing Clocking and Applying SDC Constraints
8. Runtime Flow
9. Simulating the IP
10. Validating the IP
11. Appendix A: Functional Description
12. Registers
13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide

8. Runtime Flow

To perform dynamic reconfiguration, follow these steps to ensure proper initialization and switching between IP variants:
  1. Reset the DR Controller: Reset the DR controller via the i_rst_n pin. Assert and release this reset only once, after power-up and before starting the dynamic reconfiguration sequences. Do not assert the reset afterwards.
  2. Initialize Protocol IPs: Keep protocol IPs in the DR controller group in reset until the DR controller is initialized. Detect initialization using the o_in_progress output.
  3. Dynamic Reconfiguration from IP_variant_1 to IP_variant_2:
    • Ensure the DR Controller is ready by checking o_in_progress = 0 or polling stat.ready (0x70[0]) until it is 1'b1.
    • Assert reset to protocol IPs.
    • Configure the current profile ID and target profile ID (e.g., current profile ID = 0x1, target profile ID = 0x2).
      • Program the Current Profile to Disable:
        • Set next_id_cfg[0].next_id_lo (0x00[14:0]) = 0x1 (current profile)
        • Set next_id_cfg[0].next_id_lo_act (0x00[15]) = 0x0 (neutral)
      • Program Target Profile to Enable:
        • Set next_id_cfg[0].next_id_hi (0x00[30:16]) = 0x2 (target profile)
        • Set next_id_cfg[0].next_id_hi_act (0x00[31]) = 0x1 (active)
      • End of ID List:
        • If previously used, set next_id_cfg[1].next_id_lo (0x04[14:0]) = 0x0
        • Set next_id_cfg[1].next_id_lo_act (0x04[15]) = 0x0
  4. Select the mode and trigger DR to start dynamic reconfiguration:
    • Set trigger.mode (0x50[4:3]) = 0x0
    • Set Strigger.trigger (0x50[0]) = 0x1
  5. Wait for Acknowledgment: Poll trigger.trigger (0x50[0]) until it is 1’b0.
  6. Complete Dynamic Reconfiguration: Ensure DR is completed by checking o_in_progress = 0 or polling stat.ready (0x70[0]) until it is 1'b1.
  7. Program the soft CSRs of the protocol IPs if the protocol IP is Multirate Intel® FPGA IP.
  8. De-assert the reset to protocol IPs.
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