External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 7/07/2025
Public
Document Table of Contents

3.6.1. Agilex™ 3 FPGA EMIF IP Interface Pins

Agilex™ 3 FPGAs support external memory interfaces in the high speed I/O (HSIO) bank.

The DQS (data strobe), and DQ (data) pins are listed in the device pin tables and are fixed at specific locations in the device. You must adhere to these pin locations to optimize routing, minimize skew, and maximize margins. Always check the pin table for the actual locations of the DQS and DQ pins.

You can estimate whether you have enough pins for your memory interface by performing the following steps:

  1. Determine how many read/write data pins are associated per data strobe or clock pair.
  2. Calculate the number of other memory interface pins needed, including any other clocks (write clock or memory system clock), address, command, and RZQ.
  3. Calculate the total number of I/O banks required to implement the memory interface, given that an I/O bank supports up to 96 pins.

Maximum interface width varies from device to device depending on the number of I/O pins and DQS or DQ groups available. Achievable interface width also depends on the number of address and command pins that the design requires. To ensure adequate PLL, clock, and device routing resources are available, you should always test fit the proposed pin-outs with the rest of your design in the Quartus® Prime software (with the correct I/O standard and OCT connections) before finalizing the pin-outs. Once you completed the design in the Quartus® Prime software, you may proceed to PCB sign-off. There can be interactions between modules that are illegal in the Quartus® Prime software that you might not know about unless you compile the design and use the Quartus® Prime Pin Planner.