External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
847458
Date
7/07/2025
Public
1. About the External Memory Interfaces Agilex™ 3 FPGA IP
2. Agilex™ 3 FPGA EMIF IP – Introduction
3. Agilex™ 3 FPGA EMIF IP - Configuring and Generating the IP
4. Agilex™ 3 FPGA EMIF IP – Simulating Memory IP
5. Agilex™ 3 FPGA EMIF IP - Validating the IP
6. Agilex 3 FPGA EMIF IP Debugging
7. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
A. Agilex™ 3 FPGA EMIF IP – Product Architecture
B. Agilex™ 3 FPGA EMIF IP – End-User Signals
3.1. Creating an EMIF Project
3.2. Generating and Configuring the EMIF IP
3.3. Generating HDL for Synthesis and Simulation
3.4. Generating the Synthesizable EMIF Design Example
3.5. EMIF IP LPDDR4 Parameter Descriptions
3.6. Agilex™ 3 FPGA EMIF IP Pin and Resource Planning
3.7. Compiling the Agilex™ 3 EMIF Design Example
3.8. Agilex™ 3 FPGA EMIF IP – Timing Closure
3.9. Agilex™ 3 FPGA EMIF IP – Controller Optimization
3.5.5.1. Example: DQ Pin Swizzling Within DQS Group for a x32 LPDDR4 Interface
3.5.5.2. Example: Byte Swizzling for x32 LPDDR4 Interface
3.5.5.3. Example: Combining Pin and Byte Swizzling
3.5.5.4. Example: DQ Pin Swizzling Within DQS Group for 2 Channel x16 LPDDR4 Interface
3.5.5.5. Example: Byte Swizzling for 2 Channel x16 LPDDR4 Interface
6.1. Interface Configuration Performance Issues
6.2. Functional Issue Evaluation
6.3. Timing Issue Characteristics
6.4. Evaluating FPGA Timing Issues
6.5. Verifying Memory IP Using the Signal Tap Logic Analyzer
6.6. Guidelines for Developing HDL for Traffic Generator
6.7. Debugging with the External Memory Interface Debug Toolkit
6.8. Guidelines for Traffic Generator Status Check
6.9. Hardware Debugging Guidelines
6.10. Categorizing Hardware Issues
6.11. Agilex™ 3 FPGA EMIF IP - Mailbox Support
6.9.1. Create a Simplified Design that Demonstrates the Same Issue
6.9.2. Measure Power Distribution Network
6.9.3. Measure Signal Integrity and Setup and Hold Margin
6.9.4. Vary Voltage
6.9.5. Operate at a Lower Speed
6.9.6. Determine Whether the Issue Exists in Previous Versions of Software
6.9.7. Determine Whether the Issue Exists in the Current Version of Software
6.9.8. Try A Different PCB
6.9.9. Try Other Configurations
6.9.10. Debugging Checklist
6.10.1.1. Characteristics of Signal Integrity Issues
6.10.1.2. Evaluating Signal Integrity Issues
6.10.1.3. Skew
6.10.1.4. Crosstalk
6.10.1.5. Power System
6.10.1.6. Clock Signals
6.10.1.7. Address and Command Signals
6.10.1.8. Read Data Valid Window and Eye Diagram
6.10.1.9. Write Data Valid Window and Eye Diagram
A.1.1. Agilex™ 3 EMIF Architecture: I/O Subsystem
A.1.2. Agilex™ 3 EMIF Architecture: I/O SSM
A.1.3. Agilex™ 3 EMIF Architecture: HSIO Bank
A.1.4. Agilex™ 3 EMIF Architecture: I/O Lane
A.1.5. Agilex™ 3 EMIF Architecture: Input DQS Clock Tree
A.1.6. Agilex™ 3 EMIF Architecture: PHY Clock Tree
A.1.7. Agilex™ 3 EMIF Architecture: PLL Reference Clock Networks
A.1.8. Agilex™ 3 EMIF Architecture: Clock Phase Alignment
A.1.9. User Clock in Different Core Access Modes
A.1.10. Agilex™ 3 EMIF Sequencer
A.1.11. Agilex™ 3 EMIF Controller
A.1.12. Hard Memory Controller
A.1.13. Agilex™ 3 EMIF IP for Hard Processor Subsystem (HPS)
B.1. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR4
B.2. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR4
B.3. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR4
B.4. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR4
B.5. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR4
B.6. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR4
B.7. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - LPDDR4
B.8. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR4
B.9. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4
B.10. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4
B.11. io96b0_to_hps for External Memory Interfaces (EMIF) IP - LPDDR4
B.12. io96b1_to_hps for External Memory Interfaces (EMIF) IP - LPDDR4
B.13. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR4
B.14. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4
B.15. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR4
B.16. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR4
B.17. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR4
B.18. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR4
B.19. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR4
B.20. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4
B.21. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR4
B.22. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR4
B.23. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR4
4.4. Simulating the Design Example
This topic describes how to simulate the design example in Synopsys* , and Siemens EDA simulators.
To run a simulation, navigate to the simulation directory <example_design_directory>/sim/ed_sim/ and run the simulation script of your choice.
For ModelSim* SE and Siemens* EDA QuestaSim*- Intel FPGA Edition Simulators
- At the command prompt, change the working directory to the following:
<example_design_directory>/sim/ed_sim/mentor
- Invoke vsim by typing:
vsim
The system launches a terminal window where you can run the commands described in the following steps. - Run the following command in the terminal window:
source msim_setup.tcl
- Run the following command in the terminal window:
ld_debug
- To select a signal to observe, right-click and select Add Wave from the context menu.
- To run the simulation, type:
run -all
Upon successful completion, the simulation displays the following message:
Simulation stopped due to successful completion!
For VCSMX Simulator
At the command prompt, change the working directory to the following: <example_design_directory>/sim/ed_sim/synopsys/vcsmx
Non-interactive Mode
To run a simulation in non-interactive mode, proceed as follows:
- Type the following command on a single line:
sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS=""
The system performs the simulation and displays the following message upon successful completion:
Simulation stopped due to successful completion!
Interactive Mode
To run a simulation in interactive mode, proceed as described below.
Note: If you have already generated a simv executable in non-interactive mode, delete the simv and simv.diadir files within the vcsmx folder.
- Open the vcs_setup.sh file in an editor and add a -debug_access+r command, as highlighted in the figure below:
- Compile the design example by typing:
sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" SKIP_SIM=1
- To start the simulation in interactive mode, type the following command in the terminal console:
simv -gui&