External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs
Visible to Intel only — GUID: xxk1738523312661
Ixiasoft
Visible to Intel only — GUID: xxk1738523312661
Ixiasoft
3.9.5.2. AXI to Memory Mapping
The default configuration is as follows:
<MSB | LSB> | |||||||
---|---|---|---|---|---|---|---|---|
Chip Select | Chip ID | Row | Bank | Bank Group [1] | Column [N:4] | Bank Group [0] | Column [3:0] | Datapath |
<MSB | LSB> | |||||||
---|---|---|---|---|---|---|---|---|
Chip Select | Chip ID | Row | Bank | Bank Group [1] | Column [N:4] | Bank Group [0] | Column [3:0] | Datapath |
Datapath: For a x32 or wider interface, two bits are allocated to datapath. For a x16 interface, one bit is allocated; this bit should always be set to zero.
Row/Bank/Bank Group/Column: These are allocated a number of address bits based on the requirements of the connected memory type.
Chip Select/Chip ID: These are each one bit wide and are omitted when not using multi-rank or 3DS configurations.