External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 7/07/2025
Public

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Ixiasoft

Document Table of Contents

B.17. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR4

Clock pin to the memory (channel 0).

Table 85.  Interface: mem_ck_0Interface type: conduit
Port Name Direction Description
mem_0_ck_t Output CK Clock (true) channel 0.
mem_0_ck_c Output CK Clock (complement) channel 0.