External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 7/07/2025
Public

Visible to Intel only — GUID: mus1738524914661

Ixiasoft

Document Table of Contents

5. Agilex™ 3 FPGA EMIF IP - Validating the IP

This chapter describes the steps in validating your hardware using the example design generated from the EMIF IP.

If you want to use the performance monitor, check the Enable performance monitor option in the parameter editor during example design generation.