External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

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ID 847458
Date 7/07/2025
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 3 FPGA IP 2. Agilex™ 3 FPGA EMIF IP – Introduction 3. Agilex™ 3 FPGA EMIF IP - Configuring and Generating the IP 4. Agilex™ 3 FPGA EMIF IP – Simulating Memory IP 5. Agilex™ 3 FPGA EMIF IP - Validating the IP 6. Agilex 3 FPGA EMIF IP Debugging 7. Document Revision History for External Memory Interfaces (EMIF) IP User Guide A. Agilex™ 3 FPGA EMIF IP – Product Architecture B. Agilex™ 3 FPGA EMIF IP – End-User Signals
1. About the External Memory Interfaces Agilex™ 3 FPGA IP x
1.1. Release Information
2. Agilex™ 3 FPGA EMIF IP – Introduction x
2.1. Agilex™ 3 EMIF IP Protocol and Feature Support 2.2. Protocol and Maximum Interface Width Support 2.3. Agilex 3 EMIF IP Design Flow 2.4. Agilex™ 3 EMIF IP Design Checklist
3. Agilex™ 3 FPGA EMIF IP - Configuring and Generating the IP x
3.1. Creating an EMIF Project 3.2. Generating and Configuring the EMIF IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Synthesizable EMIF Design Example 3.5. EMIF IP LPDDR4 Parameter Descriptions 3.6. Agilex™ 3 FPGA EMIF IP Pin and Resource Planning 3.7. Compiling the Agilex™ 3 EMIF Design Example 3.8. Agilex™ 3 FPGA EMIF IP – Timing Closure 3.9. Agilex™ 3 FPGA EMIF IP – Controller Optimization
3.4. Generating the Synthesizable EMIF Design Example x
3.4.1. Synthesis Design Example
3.5. EMIF IP LPDDR4 Parameter Descriptions x
3.5.1. High-level Configuration Tab 3.5.2. Advanced: Memory Timing Tab 3.5.3. Advanced: Analog Overrides Tab 3.5.4. Example Design Tab 3.5.5. Configuring DQ Pin Swizzling
3.5.5. Configuring DQ Pin Swizzling x
3.5.5.1. Example: DQ Pin Swizzling Within DQS Group for a x32 LPDDR4 Interface 3.5.5.2. Example: Byte Swizzling for x32 LPDDR4 Interface 3.5.5.3. Example: Combining Pin and Byte Swizzling 3.5.5.4. Example: DQ Pin Swizzling Within DQS Group for 2 Channel x16 LPDDR4 Interface 3.5.5.5. Example: Byte Swizzling for 2 Channel x16 LPDDR4 Interface
3.6. Agilex™ 3 FPGA EMIF IP Pin and Resource Planning x
3.6.1. Agilex™ 3 FPGA EMIF IP Interface Pins 3.6.2. Pin Guidelines for Agilex™ 3 FPGA EMIF IP 3.6.3. Agilex™ 3 FPGA EMIF IP Resources
3.6.1. Agilex™ 3 FPGA EMIF IP Interface Pins x
3.6.1.1. Estimating Pin Requirements 3.6.1.2. LPDDR4 Component Options 3.6.1.3. Maximum Number of Interfaces 3.6.1.4. Address and Command Pin Placement for LPDDR4 3.6.1.5. LPDDR4 Data Width Mapping 3.6.1.6. Pin Placement for Agilex™ 3 EMIF IP
3.6.2. Pin Guidelines for Agilex™ 3 FPGA EMIF IP x
3.6.2.1. General Guidelines 3.6.2.2. Specific Pin Connection Requirements 3.6.2.3. Command and Address Signals 3.6.2.4. Clock Signals 3.6.2.5. Pin Swizzling Guidelines
3.6.3. Agilex™ 3 FPGA EMIF IP Resources x
3.6.3.1. OCT 3.6.3.2. PLL
3.8. Agilex™ 3 FPGA EMIF IP – Timing Closure x
3.8.1. Timing Closure 3.8.2. Timing Analysis 3.8.3. PHY or Core 3.8.4. Optimizing Timing
3.9. Agilex™ 3 FPGA EMIF IP – Controller Optimization x
3.9.1. Optimizing Efficiency for Secondary Controller 3.9.2. Interface Standard 3.9.3. Bank Management Efficiency 3.9.4. Data Transfer 3.9.5. Improving Controller Efficiency
3.9.5. Improving Controller Efficiency x
3.9.5.1. Series of Reads or Writes 3.9.5.2. AXI to Memory Mapping 3.9.5.3. Controller Performance Profile
4. Agilex™ 3 FPGA EMIF IP – Simulating Memory IP x
4.1. Simulation Walkthrough 4.2. Generating the EMIF Design Example for Simulation 4.3. Simulation Design Example 4.4. Simulating the Design Example
4.1. Simulation Walkthrough x
4.1.1. Calibration 4.1.2. Simulation Scripts 4.1.3. Functional Simulation with Verilog HDL
5. Agilex™ 3 FPGA EMIF IP - Validating the IP x
5.1. Validating the Design Example with the Test Engine IP 5.2. Checking the EMIF Design Example with the Performance Monitor
6. Agilex 3 FPGA EMIF IP Debugging x
6.1. Interface Configuration Performance Issues 6.2. Functional Issue Evaluation 6.3. Timing Issue Characteristics 6.4. Evaluating FPGA Timing Issues 6.5. Verifying Memory IP Using the Signal Tap Logic Analyzer 6.6. Guidelines for Developing HDL for Traffic Generator 6.7. Debugging with the External Memory Interface Debug Toolkit 6.8. Guidelines for Traffic Generator Status Check 6.9. Hardware Debugging Guidelines 6.10. Categorizing Hardware Issues 6.11. Agilex™ 3 FPGA EMIF IP - Mailbox Support
6.1. Interface Configuration Performance Issues x
6.1.1. Interface Configuration Bottleneck and Efficiency Issues
6.2. Functional Issue Evaluation x
6.2.1. Altera IP Memory Model 6.2.2. Vendor Memory Model 6.2.3. Transcript Window Messages
6.4. Evaluating FPGA Timing Issues x
6.4.1. Evaluating External Memory Interface Timing Issues
6.7. Debugging with the External Memory Interface Debug Toolkit x
6.7.1. Prerequisites for Using the EMIF Debug Toolkit 6.7.2. Configuring a Design to Use the Debug Toolkit 6.7.3. Launching the EMIF Debug Toolkit 6.7.4. Using the EMIF Debug Toolkit
6.7.2. Configuring a Design to Use the Debug Toolkit x
6.7.2.1. Generating a Design Example with the Debug Toolkit
6.7.4. Using the EMIF Debug Toolkit x
6.7.4.1. Running Re-Calibration 6.7.4.2. Running the Test Engine 6.7.4.3. Generating Traffic with the Test Engine IP
6.8. Guidelines for Traffic Generator Status Check x
6.8.1. Status Check Using the Signal Tap Logic Analyzer 6.8.2. Exporting the Status Interface to the Top-Level Design
6.9. Hardware Debugging Guidelines x
6.9.1. Create a Simplified Design that Demonstrates the Same Issue 6.9.2. Measure Power Distribution Network 6.9.3. Measure Signal Integrity and Setup and Hold Margin 6.9.4. Vary Voltage 6.9.5. Operate at a Lower Speed 6.9.6. Determine Whether the Issue Exists in Previous Versions of Software 6.9.7. Determine Whether the Issue Exists in the Current Version of Software 6.9.8. Try A Different PCB 6.9.9. Try Other Configurations 6.9.10. Debugging Checklist
6.10. Categorizing Hardware Issues x
6.10.1. Signal Integrity Issues 6.10.2. Hardware and Calibration Issues
6.10.1. Signal Integrity Issues x
6.10.1.1. Characteristics of Signal Integrity Issues 6.10.1.2. Evaluating Signal Integrity Issues 6.10.1.3. Skew 6.10.1.4. Crosstalk 6.10.1.5. Power System 6.10.1.6. Clock Signals 6.10.1.7. Address and Command Signals 6.10.1.8. Read Data Valid Window and Eye Diagram 6.10.1.9. Write Data Valid Window and Eye Diagram
6.10.2. Hardware and Calibration Issues x
6.10.2.1. Verifying High-Level Configuration 6.10.2.2. Verifying Memory Timing Parameters 6.10.2.3. Verifying the Correct Memory Component Installed 6.10.2.4. Debugging Intermittent Issues
6.11. Agilex™ 3 FPGA EMIF IP - Mailbox Support x
6.11.1. Agilex™ 3 Mailbox Structure and Register Definitions 6.11.2. Accessing Read-Only Registers 6.11.3. Sending a Mailbox Command 6.11.4. IOSSM Mailbox Access Script
6.11.1. Agilex™ 3 Mailbox Structure and Register Definitions x
6.11.1.1. Mailbox Supported Commands 6.11.1.2. Mailbox Command Definitions 6.11.1.3. ECC Syndrome Codes 6.11.1.4. ECC Error Handling
6.11.2. Accessing Read-Only Registers x
6.11.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Through Read-Only Registers 6.11.2.2. Example 2: Reading the Memory Clock Frequency for an Interface
6.11.3. Sending a Mailbox Command x
6.11.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox 6.11.3.2. Example 4: Sending ECC_INJECT_ERROR Using the Mailbox and Reading ECC Error Status, ECC Error Buffer Registers
6.11.4. IOSSM Mailbox Access Script x
6.11.4.1. Mailbox Script Overview 6.11.4.2. Running the Mailbox Script
6.11.4.1. Mailbox Script Overview x
6.11.4.1.1. mb_iossm_command.tcl 6.11.4.1.2. mb_user_input.tcl
A. Agilex™ 3 FPGA EMIF IP – Product Architecture x
A.1. Agilex™ 3 EMIF Architecture: Introduction
A.1. Agilex™ 3 EMIF Architecture: Introduction x
A.1.1. Agilex™ 3 EMIF Architecture: I/O Subsystem A.1.2. Agilex™ 3 EMIF Architecture: I/O SSM A.1.3. Agilex™ 3 EMIF Architecture: HSIO Bank A.1.4. Agilex™ 3 EMIF Architecture: I/O Lane A.1.5. Agilex™ 3 EMIF Architecture: Input DQS Clock Tree A.1.6. Agilex™ 3 EMIF Architecture: PHY Clock Tree A.1.7. Agilex™ 3 EMIF Architecture: PLL Reference Clock Networks A.1.8. Agilex™ 3 EMIF Architecture: Clock Phase Alignment A.1.9. User Clock in Different Core Access Modes A.1.10. Agilex™ 3 EMIF Sequencer A.1.11. Agilex™ 3 EMIF Controller A.1.12. Hard Memory Controller A.1.13. Agilex™ 3 EMIF IP for Hard Processor Subsystem (HPS)
A.1.3. Agilex™ 3 EMIF Architecture: HSIO Bank x
A.1.3.1. Narrow Read Transfer Support A.1.3.2. HSIO Sub-Bank Usage
A.1.12. Hard Memory Controller x
A.1.12.1. Hard Memory Controller Features
A.1.13. Agilex™ 3 EMIF IP for Hard Processor Subsystem (HPS) x
A.1.13.1. Restrictions on I/O Bank Usage for Agilex™ 3 EMIF IP with HPS A.1.13.2. Using the Legacy EMIF Debug Toolkit with Agilex™ 3 HPS Interfaces
B. Agilex™ 3 FPGA EMIF IP – End-User Signals x
B.1. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR4 B.2. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR4 B.3. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR4 B.4. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR4 B.5. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR4 B.6. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR4 B.7. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - LPDDR4 B.8. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR4 B.9. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4 B.10. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4 B.11. io96b0_to_hps for External Memory Interfaces (EMIF) IP - LPDDR4 B.12. io96b1_to_hps for External Memory Interfaces (EMIF) IP - LPDDR4 B.13. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR4 B.14. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4 B.15. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR4 B.16. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR4 B.17. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR4 B.18. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR4 B.19. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR4 B.20. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4 B.21. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR4 B.22. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR4 B.23. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR4
1. About the External Memory Interfaces Agilex™ 3 FPGA IP
2. Agilex™ 3 FPGA EMIF IP – Introduction
3. Agilex™ 3 FPGA EMIF IP - Configuring and Generating the IP
4. Agilex™ 3 FPGA EMIF IP – Simulating Memory IP
5. Agilex™ 3 FPGA EMIF IP - Validating the IP
6. Agilex 3 FPGA EMIF IP Debugging
7. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
A. Agilex™ 3 FPGA EMIF IP – Product Architecture
B. Agilex™ 3 FPGA EMIF IP – End-User Signals

3.5.2. Advanced: Memory Timing Tab

The following figure shows the Advanced: Memory Timing tab.

This tab contains two groups of parameters: Overrides and Values. The tables which follow provide descriptions of the parameters on this tab.

Figure 15. Advanced Memory Timing Tab
Table 8.  Group: Advanced: Memory Timing / Overrides / JEDEC_TABLE
Parameter Name Description
JEDEC Parameter

Name of JEDEC Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are: MEM_CL_CYC, MEM_CWL_CYC, MEM_RD_POSTAMBLE_CYC, MEM_WR_POSTAMBLE_CYC, MEM_TSR_NS, MEM_TRFCAB_NS, MEM_TRFCPB_NS, MEM_TXSR_NS, MEM_TXP_NS, MEM_TCCD_NS, MEM_TRTP_NS, MEM_TRCD_NS, MEM_TRPPB_NS, MEM_TRPAB_NS, MEM_TRAS_NS, MEM_TWR_NS, MEM_TWTR_NS, MEM_TRRD_NS, MEM_TPPD_CYC, MEM_TFAW_NS, MEM_TRC_NS, MEM_TREFW_NS, MEM_MINNUMREFSREQ, MEM_TREFI_NS, MEM_TCKE_NS, MEM_TCMDCKE_NS, MEM_TCKELCK_NS, MEM_TCSCKE_NS, MEM_TCKCKEH_NS, MEM_TCSCKEH_NS, MEM_TMRWCKEL_NS, MEM_TZQCKE_NS, MEM_TMRR_NS, MEM_TMRW_NS, MEM_TMRD_NS, MEM_TESCKE_NS, MEM_TZQCAL_NS, MEM_TZQLAT_NS, MEM_TDQSCK_MAX_NS, MEM_TDQSCK_MIN_NS, MEM_TCKCKEL_NS, MEM_TCKELCMD_NS, MEM_TCKEHCMD_NS

(Identifier: JEDEC_OVERRIDE_TABLE_PARAM_NAME)
Table 9.  Group: Advanced: Memory Timing / Values
Parameter Name Description
Read Latency

Read Latency of the memory device in clock cycles.

(Identifier: MEM_CL_CYC)
Write Latency

Write Latency in clock cycles.

(Identifier: MEM_CWL_CYC)
Read Postamble Cycles

Duration of read postamble in cycles.

(Identifier: MEM_RD_POSTAMBLE_CYC)
Write Postamble Cycles

Duration of write postamble in cycles.

(Identifier: MEM_WR_POSTAMBLE_CYC)
tSR

Minimum duration (Entry to Exit) of Self Refresh in nanoseconds.

(Identifier: MEM_TSR_NS)
tRFCab

All-Bank Refresh Cycle Time in nanoseconds.

(Identifier: MEM_TRFCAB_NS)
tRFCpb

Per-Bank Refresh Cycle Time in nanoseconds.

(Identifier: MEM_TRFCPB_NS)
tXSR

Self-Refresh Exit to Next Valid Command Delay Time in nanoseconds.

(Identifier: MEM_TXSR_NS)
tXP

Exit Power-Down to Next Valid Command Delay Time in nanoseconds.

(Identifier: MEM_TXP_NS)
tCCD

CAS-to-CAS Delay in nanoseconds.

(Identifier: MEM_TCCD_NS)
tRTP

Internal READ to PRECHARGE Command Delay Time in nanoseconds.

(Identifier: MEM_TRTP_NS)
tRCD

RAS-to-CAS Delay in nanoseconds.

(Identifier: MEM_TRCD_NS)
tRPpb

Per-Bank Precharge Time in nanoseconds.

(Identifier: MEM_TRPPB_NS)
tRPab

All-Bank Precharge Time in nanoseconds.

(Identifier: MEM_TRPAB_NS)
tRAS

Row Active Time in nanoseconds.

(Identifier: MEM_TRAS_NS)
tWR

Write Recovery Time in nanoseconds.

(Identifier: MEM_TWR_NS)
tWTR

Write-to-Read Delay in nanoseconds.

(Identifier: MEM_TWTR_NS)
tRRD

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time in nanoseconds.

(Identifier: MEM_TRRD_NS)
tFAW

Four-bank ACTIVE window time in nanoseconds.

(Identifier: MEM_TFAW_NS)
tRC

Activate-to-Activate command period (same bank) in nanoseconds.

(Identifier: MEM_TRC_NS)
tREFW

Refresh window time in nanoseconds.

(Identifier: MEM_TREFW_NS)
Min Number of Refs Reqd

Minimum Number of Refreshes Required.

(Identifier: MEM_MINNUMREFSREQ)
tREFI

Refresh Interval Time in nanoseconds.

(Identifier: MEM_TREFI_NS)
tCKE

CKE Minimum Pulse Width time in nanoseconds.

(Identifier: MEM_TCKE_NS)
tCMDCKE

Delay from valid command to power-down-entry (CKE low) in nanoseconds.

(Identifier: MEM_TCMDCKE_NS)
tCKELCK

Valid clock requirement after power-down-entry in nanoseconds.

(Identifier: MEM_TCKELCK_NS)
tCSCKE

Valid CS requirement before power-down-entry (CKE low) in nanoseconds.

(Identifier: MEM_TCSCKE_NS)
tCKCKEH

Valid clock requirement before power-down-exit in nanoseconds.

(Identifier: MEM_TCKCKEH_NS)
tCSCKEH

Valid CS requirement before power-down-exit (CKE high) in nanoseconds.

(Identifier: MEM_TCSCKEH_NS)
tMRWCKEL

Delay from MRW command to power-down-entry (CKE low) in nanoseconds.

(Identifier: MEM_TMRWCKEL_NS)
tZQCKE

Delay from ZQCal Start command to power-down-entry (CKE low) in nanoseconds.

(Identifier: MEM_TZQCKE_NS)
tMRR

Mode Register Read Command Period Time in nanoseconds.

(Identifier: MEM_TMRR_NS)
tMRW

Mode Register Write Command Period Time in nanoseconds.

(Identifier: MEM_TMRW_NS)
tMRD

Mode Register Set Command Period Time in nanoseconds.

(Identifier: MEM_TMRD_NS)
tESCKE

Delay from SRE command to CKE Input low in nanoseconds.

(Identifier: MEM_TESCKE_NS)
tZQCAL

ZQ calibration time in nanoseconds.

(Identifier: MEM_TZQCAL_NS)
tZQLAT

ZQcal Latch time in nanoseconds.

(Identifier: MEM_TZQLAT_NS)
tDQSCK_MAX

Maximum DQS output access time from CK in nanoseconds.

(Identifier: MEM_TDQSCK_MAX_NS)
tDQSCK_MIN

Minimum DQS output access time from CK in nanoseconds.

(Identifier: MEM_TDQSCK_MIN_NS)
tCKCKEL

Clock valid requirements after power-down-entry (CKE low) in nanoseconds.

(Identifier: MEM_TCKCKEL_NS)
tCKELCMD

Valid command requirement after CKE input low in nanoseconds.

(Identifier: MEM_TCKELCMD_NS)
tCKEHCMD

Valid command requirement after CKE input high in nanoseconds.

(Identifier: MEM_TCKEHCMD_NS)
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