DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 12/20/2024
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. Design Example: DisplayPort SST Parallel Loopback without PCR 4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface 5. Design Example: DisplayPort SST TX-Only Design 6. Design Example: DisplayPort SST RX-Only Design 7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating ELF File 1.7. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Design Components 2.2. Clocking Scheme 2.3. Interface Signals and Parameters 2.4. Simulation Testbench
3. Design Example: DisplayPort SST Parallel Loopback without PCR x
3.1. Features 3.2. Functional Description 3.3. DisplayPort SST Parallel Loopback without PCR with Duplex Mode 3.4. DisplayPort SST Parallel Loopback without PCR with Dual-Simplex Mode 3.5. GTS DisplayPort PHY Dual Simplex Mode IP Generation Flow
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface x
4.1. Features 4.2. Functional Description
5. Design Example: DisplayPort SST TX-Only Design x
5.1. Features 5.2. Functional Description
6. Design Example: DisplayPort SST RX-Only Design x
6.1. Features 6.2. Functional Description
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. Design Example: DisplayPort SST Parallel Loopback without PCR
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface
5. Design Example: DisplayPort SST TX-Only Design
6. Design Example: DisplayPort SST RX-Only Design
7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

1.3. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in Quartus® Prime software to generate the design example.
Note: You need a Nios® V evaluation license. Refer to the Nios® V Processor Licensing topic in the Nios® V Embedded Processor Design Handbook.
Figure 3. Generating the Design Flow
  1. To generate a design example, follow these steps:
    • For Quartus® Prime Pro Edition running in a Windows environment:
      1. Open Nios® V Command Shell from the Windows search path.
      2. Run "quartus" in Nios® V Command Shell to open Quartus® Prime Pro Edition.
    • For Quartus® Prime Pro Edition running in a Linux environment:
      1. cd to <Quartus installation path>/niosv/bin and run "niosv-shell".
      2. Run "quartus" to open Quartus® Prime Pro Edition.
  2. Select Tools > IP Catalog, and select Agilex™ 5 as the target device family.
    Note: The design example only supports Agilex™ 5 devices.
  3. In the IP Catalog, locate and double-click DisplayPort Intel® FPGA IP . The New IP Variation window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Select an Agilex™ 5 device in the Device field, or keep the default Quartus® Prime software device selection.
  6. Click OK. The parameter editor appears.
  7. Configure the desired parameter for TX and RX.
    Note: The Nios® V software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios® V terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  8. Under the Design Example tab, select one of the following options:
    • DisplayPort SST Parallel Loopback without PCR
    • DisplayPort SST Parallel Loopback with AXIS Video Interface
    • DisplayPort SST TX-Only
    • DisplayPort SST RX-Only
  9. Select Synthesis to generate the hardware design example.
  10. For Target Development Kit, select either:
    • Intel Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Premium Development Kit
    • Intel Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Modular Development Kit
    This selection changes the target device selected in step 5 to match the device on the development kit. The default device for both is A5ED065BB32AE6SR0.
  11. Click Generate Design Example.
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