DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 12/20/2024
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. Design Example: DisplayPort SST Parallel Loopback without PCR 4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface 5. Design Example: DisplayPort SST TX-Only Design 6. Design Example: DisplayPort SST RX-Only Design 7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating ELF File 1.7. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Design Components 2.2. Clocking Scheme 2.3. Interface Signals and Parameters 2.4. Simulation Testbench
3. Design Example: DisplayPort SST Parallel Loopback without PCR x
3.1. Features 3.2. Functional Description 3.3. DisplayPort SST Parallel Loopback without PCR with Duplex Mode 3.4. DisplayPort SST Parallel Loopback without PCR with Dual-Simplex Mode 3.5. GTS DisplayPort PHY Dual Simplex Mode IP Generation Flow
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface x
4.1. Features 4.2. Functional Description
5. Design Example: DisplayPort SST TX-Only Design x
5.1. Features 5.2. Functional Description
6. Design Example: DisplayPort SST RX-Only Design x
6.1. Features 6.2. Functional Description
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. Design Example: DisplayPort SST Parallel Loopback without PCR
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface
5. Design Example: DisplayPort SST TX-Only Design
6. Design Example: DisplayPort SST RX-Only Design
7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

1.7. DisplayPort Intel® FPGA IP Design Example Parameters

The following table lists the DisplayPort Intel® FPGA IP design example parameters for Agilex™ 5 devices:

Table 2.  DisplayPort Intel® FPGA IP Design Example Parameters for Agilex™ 5 Devices
Parameter Value Description
Available Design Example
Select Design
  • None
  • DisplayPort SST Parallel Loopback without PCR
  • DisplayPort SST Parallel Loopback with AXIS Video Interface
  • DisplayPort RX-only
  • DisplayPort TX-only
 Select the design example to be generated.
  • None: No design example is available for the current parameter selection.
  • DisplayPort SST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter.
  • DisplayPort SST Parallel Loopback with AXIS Video Interface: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source with AXIS Video interface when Enable Active Video Data Protocols is set to AXIS-VVP Full.
  • DisplayPort RX-only: This design example demonstrates an RX-only design. The Enable Video Input Image Port parameter must be disabled. The design example software will report the RX link status.
  • DisplayPort TX-only: This design example demonstrates a TX-only design. The Enable Video Input Image Port parameter must be disabled. The design example software reports the TX link status. The design will output color bars in 1080p format.
    Note: The hardware support is only available for the DisplayPort TX-only variant.
Transceiver Construction
  • Duplex
  • Dual-Simplex
 When an design example includes both RX and TX instances, you can select two transceiver variants to demonstrate different Agilex™ 5 design flows.
Note: Dual-Simplex only supports SCT (Simulation, Compilation and Timing).
Transceiver Clock
  • PMA Direct
  • System PLL
 To enable more flexible clocking schemes, you can generate the design example using either the System PLL or the PMA Direct clocking methods.
Design Example Files
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.
Synthesis On, Off Turn on this option to generate the necessary files for Quartus® Prime compilation and hardware design.
Generated HDL Format
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
Target Development Kit
Select Board
  • No Development Kit
  • Intel Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Premium Development Kit
  • Custom Development Kit
  • Intel Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Modular Development Kit
Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Intel Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Premium Development Kit: This option automatically sets the project's target device to the A5ED065BB32AE6SR0. You may change the target device using the Change Target Device parameter, but Intel strongly recommends that you do not override the target device. If you require a different device, select the Custom Development Kit option. The IP core sets all pin assignments according to the development kit.
  • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with an Intel FPGA. Set the project's target device to match the current project's target device, and modify the pin assignments as necessary.
  • Intel Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Modular Development Kit: This option automatically sets the project's target device to the A5ED065BB32AE6SR0. You may change the target device using the Change Target Device parameter, but Intel strongly recommends that you do not override the target device. If you require a different device, select the Custom Development Kit option. The IP core sets all pin assignments according to the development kit.
FMC Revision
  • Bitec Rev 8
  • Devkit Connector (No FMC)
 Choose the physical interface location for the DisplayPort connecters:
  • Bitec Rev 8: This option selects the FMC card from Bitec Revision 8 to provide the DisplayPort connectors.
  • Devkit Connector (No FMC): This option is only available on the Modular Development Kit and enables the carrier board DisplayPort connectors. No FMC is required to be fitted.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.
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