DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 12/20/2024
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. Design Example: DisplayPort SST Parallel Loopback without PCR 4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface 5. Design Example: DisplayPort SST TX-Only Design 6. Design Example: DisplayPort SST RX-Only Design 7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating ELF File 1.7. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Design Components 2.2. Clocking Scheme 2.3. Interface Signals and Parameters 2.4. Simulation Testbench
3. Design Example: DisplayPort SST Parallel Loopback without PCR x
3.1. Features 3.2. Functional Description 3.3. DisplayPort SST Parallel Loopback without PCR with Duplex Mode 3.4. DisplayPort SST Parallel Loopback without PCR with Dual-Simplex Mode 3.5. GTS DisplayPort PHY Dual Simplex Mode IP Generation Flow
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface x
4.1. Features 4.2. Functional Description
5. Design Example: DisplayPort SST TX-Only Design x
5.1. Features 5.2. Functional Description
6. Design Example: DisplayPort SST RX-Only Design x
6.1. Features 6.2. Functional Description
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. Design Example: DisplayPort SST Parallel Loopback without PCR
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface
5. Design Example: DisplayPort SST TX-Only Design
6. Design Example: DisplayPort SST RX-Only Design
7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

2.2. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel® FPGA IP design example.

Figure 7.  Agilex™ 5 DisplayPort Transceiver Clocking Scheme
Table 7.  Clocking Scheme Signals
Clock in diagram Description
SysPLL refclk

The GTS System PLL can reference any clock frequency that the System PLL can divide to produce the desired output frequency.

In this design example, system_pll_clk_link and rx/tx refclk_link share the same 150 MHz refclk.

It must be a free running clock which is connected from a dedicated transceiver reference clock pin to the input clock port of System PLL Clocks IP, before connecting the corresponding output port to DisplayPort PHY Top.

Transceiver Refclk The GTS PMA reference clocks must come from a free-running 150 MHz refclk pin. The PMA generates all supported DisplayPort line rates from this clock. This clock pin may be shared with the SystemPLL when enabled.
system_pll_clk_link

The minimum System PLL output frequency to support all DisplayPort rates is 320 MHz.

This design example uses a 700 MHz (highest) output frequency so that SysPLL refclk can be shared with rx/tx refclk_link, which is 150 MHz.

rx_cdr_refclk_link / tx_pll_refclk_link RX CDR and TX PLL Link refclk which is fixed to 150 MHz to support all DisplayPort data rates.
rx_ls_clkout / tx_ls_clkout

DisplayPort Link Speed Clock to clock DisplayPort IP core. The frequency is equivalent to Data Rate divided by parallel data width.

Example:

Frequency = data rate / data width

For HBR3:

= 8.1G (HBR3) / 40 bits

= 202.5 MHz

For UHBR10:

= 10G (UHBR10) / 64 bits

= 312.5 MHz
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