DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 12/20/2024
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. Design Example: DisplayPort SST Parallel Loopback without PCR 4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface 5. Design Example: DisplayPort SST TX-Only Design 6. Design Example: DisplayPort SST RX-Only Design 7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating ELF File 1.7. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Design Components 2.2. Clocking Scheme 2.3. Interface Signals and Parameters 2.4. Simulation Testbench
3. Design Example: DisplayPort SST Parallel Loopback without PCR x
3.1. Features 3.2. Functional Description 3.3. DisplayPort SST Parallel Loopback without PCR with Duplex Mode 3.4. DisplayPort SST Parallel Loopback without PCR with Dual-Simplex Mode 3.5. GTS DisplayPort PHY Dual Simplex Mode IP Generation Flow
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface x
4.1. Features 4.2. Functional Description
5. Design Example: DisplayPort SST TX-Only Design x
5.1. Features 5.2. Functional Description
6. Design Example: DisplayPort SST RX-Only Design x
6.1. Features 6.2. Functional Description
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. Design Example: DisplayPort SST Parallel Loopback without PCR
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface
5. Design Example: DisplayPort SST TX-Only Design
6. Design Example: DisplayPort SST RX-Only Design
7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

2. DisplayPort Intel® FPGA IP Design Examples

The DisplayPort Intel® FPGA IP design example for Agilex™ 5 device demonstrates the functionality of the DisplayPort TX instance. Full SCT (Simulation, Compilation, and Timing) support is provided for both the RX and TX instances. However, note that the current Quartus® Prime Pro Edition Software version 24.3 supports only the TX instance in hardware.

The DisplayPort Intel® FPGA IP TX-only design example demonstrates the DisplayPort source transmitting a fixed video resolution.

The DisplayPort Intel® FPGA IP RX-only design example demonstrates the DisplayPort sink receiving video frame from external sources.

Table 3.  DisplayPort Intel® FPGA IP Design Example for Agilex™ 5 Device
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST parallel loopback without PCR DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10, UHBR13.5
  • Duplex
  • Dual Simplex
 Parallel without PCR
DisplayPort SST parallel loopback with AXIS Video Interface DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10, UHBR13.5
  • Duplex
  • Dual Simplex
 Parallel with AXIS Video Interface
DisplayPort SST TX-only DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10, UHBR13.5 Simplex —
DisplayPort SST RX-only DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10, UHBR13.5 Simplex —
Note:
  • The Bitec Rev8 FMC can handle High Bit Rates (HBR) up to 8.1 Gbps as per DisplayPort 1.4 standards, while the native connectors on the Modular Development Kit support Ultra-High Bit Rates (UHBR) up to 13.5 Gbps. Always use the native connectors for designs targeting UHBR rates.
  • The Agilex 5E part transceivers operate up to 17G, which is why UHBR20 is not supported on Agilex 5E parts.

Section Content
Design Components
Clocking Scheme
Interface Signals and Parameters
Simulation Testbench

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