DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 12/20/2024
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. Design Example: DisplayPort SST Parallel Loopback without PCR 4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface 5. Design Example: DisplayPort SST TX-Only Design 6. Design Example: DisplayPort SST RX-Only Design 7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating ELF File 1.7. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Design Components 2.2. Clocking Scheme 2.3. Interface Signals and Parameters 2.4. Simulation Testbench
3. Design Example: DisplayPort SST Parallel Loopback without PCR x
3.1. Features 3.2. Functional Description 3.3. DisplayPort SST Parallel Loopback without PCR with Duplex Mode 3.4. DisplayPort SST Parallel Loopback without PCR with Dual-Simplex Mode 3.5. GTS DisplayPort PHY Dual Simplex Mode IP Generation Flow
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface x
4.1. Features 4.2. Functional Description
5. Design Example: DisplayPort SST TX-Only Design x
5.1. Features 5.2. Functional Description
6. Design Example: DisplayPort SST RX-Only Design x
6.1. Features 6.2. Functional Description
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. Design Example: DisplayPort SST Parallel Loopback without PCR
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface
5. Design Example: DisplayPort SST TX-Only Design
6. Design Example: DisplayPort SST RX-Only Design
7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

3.3. DisplayPort SST Parallel Loopback without PCR with Duplex Mode

For designs with supported HSSI IP targeting Agilex 5 FPGAs, you can generate a Duplex PHY. If your board layout supports Duplex, instantiate a Duplex PHY to simplify your design. This approach eliminates the need for the DS tool and its complex work flow.
To generate a Duplex design example, go to the Design Example IP tab, expand PHY Structure, and select Transceiver Construction, as shown below. This option is hidden for Receiver or Transmitter only design examples as the Dual Simplex tool does not apply to these configurations.
Figure 10. Duplex Mode

Use Duplex mode when both the TX and RX transceivers handle the DisplayPort protocol. This approach eliminates the need for dual-simplex tools and HSSI Generation logic, resulting in a simpler design flow for supported configurations.

All RX/TX design examples enable users to explore both Duplex and Dual Simplex flows.

The following figure illustrates a Duplex PHY with one instance of Direct PHY_GTS embedded within the GTS DisplayPort PHY Altera® FPGA IP.
Figure 11. Duplex PHY

DisplayPort PHY Duplex Mode IP Generation Flow

When you generate a duplex mode design example, a single transceiver core appears in the top-level Verilog of the design example, as shown below:
Figure 12. Duplex PHY IP Top-Level Module
The DS tool is grayed out since the design does not include any simplex IPs.
Figure 13. Dual Simplex (DS) Assignment Editor
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