Visible to Intel only — GUID: rmi1710506807375
Ixiasoft
1.1. H2D ST to D2H ST Loopback Design Example
The H2D ST to D2H ST Loopback design example is designed to highlight Scalable Scatter-Gather DMA Intel® FPGA IP functionality. In this design example, the data from the Host is loopbacked from the H2D ST device port to the D2H ST device port and written back to the Host memory for application software comparison.
The design example automatically creates the files necessary to simulate and compile in the Quartus® Prime software.