Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

ID 823179
Date 1/27/2025
Public

1. Design Example Description

Updated for:
Intel® Quartus® Prime Design Suite 24.3.1
IP Version 1.1.3
The Scalable Scatter-Gather DMA Intel® FPGA IP provides a design example and simulation testbench that supports compilation and simulation.

The following table lists the terms and definitions used in this document.

Table 1.  Terms and Definitions
Term Definition
API Application Programming Interface
APP2SS Application to PCIe* Subsystem
ATT Address Translation Table
AXI-4 Advanced extensible Interface associated with AMBA version 4.0
AXI-4 Lite AMBA AXI-4 Lite Memory Map Interface
AXI-ST AXI Streaming
BAM Bursting Manager
BAS Bursting Subordinate
CEB Configuration Extension Bus
CSR Control Status Register
D2H Device to Host
DMA Direct Memory Access
DPDK Data Path Development Kit
EOF End of a File (or packet) for streaming
File (or Packet) A group of descriptors defined by SOF and EOF bits of the descriptor for the streaming. At the AXI-ST user interface, a file (or packet) is marked using TUSER.SOF (Optional for SOF) and TLAST (as EOF).
FLR Function Level Reset
H2D Host to Device
HIDX Queue Insert Index (Pointer)
HIP Hard IP
HPS Hard Processor System
IP Intellectual Property
MCDMA Multi-Channel Direct Memory Access
MPS Maximum Payload Size
MRRS Maximum Read Request Size
MSI Message Signaled Interrupt
MSI-X Message Signaled Interrupt - Extended
PBA Pending Bit Array
PCIe* Peripheral Component Interconnect Express ( PCI Express* )
PD Packet Descriptor
PF Physical Function
PMD Poll Mode Driver
QID Queue Identification
QOS Quality of Service
SoC System on Chip
SOF Start of a File (or packet) for streaming
SR-IOV Single Root I/O Virtualization
SS Subsystem
SS2APP PCIe* Subsystem to Application
TIDX Queue Extract Index (Pointer)
TLP Transaction Layer Protocol
VF Virtual Function

The following table presents an overview of the design example supported by the Scalable Scatter-Gather DMA Intel® FPGA IP:

Table 2.  Design Example Overview
IP Mode Design Example Mode Compilation Simulation Hardware
DMA PCIe* Mode Multiport H2D-ST to D2H-ST Loopback & H2D MM to Onchip Memory Supported Supported Not supported
DMA SoC Mode H2D ST to D2H ST Single Port Loopback Supported Supported Not supported

You can generate the design example from the Example Design tab of the Scalable Scatter-Gather DMA IP Parameter Editor.