Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

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ID 823179
Date 1/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide
1. Design Example Description x
1.1. H2D ST to D2H ST Loopback Design Example
1.1. H2D ST to D2H ST Loopback Design Example x
1.1.1. DMA PCIe* Mode Design Example 1.1.2. DMA SoC Mode Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. DMA SoC Mode Example Design 2.3.2. DMA PCIe Mode Example Design
2.3.2. DMA PCIe Mode Example Design x
2.3.2.1. Running Simulation using VCS* MX 2.3.2.2. Running Simulation Using QuestaSim*
2.4. Testbench x
2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
1. Design Example Description
2. Quick Start Guide
3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

1.1.1. DMA PCIe* Mode Design Example

Figure 1. H2D ST to D2H ST Loopback & H2D MM to Onchip Memory

This design example includes the following components:

  • The generated Scalable Scatter-Gather DMA IP with the parameters you specified. With device-side packet loopback, the Host to Device (H2D) ST data stream is looped back to the Device to Host (D2H) ST device port. When you enable the H2D MM port, it connects to On-Chip Memory II IP.
  • The GTS AXI Streaming IP for PCI Express* in Endpoint mode interacts with the root complex/switch at the other end of the PCIe* link and translates the data from the PCIe* link into AXI-ST data format to SSGDMA IP and vice versa.
  • The GTS Reset Sequencer IP is required for GTS AXI Streaming IP for PCI Express* implementation. The o_pma_cu_clk output of this IP drives the i_flux_clk input of the GTS AXI Streaming IP for PCI Express* .
  • The GTS System PLL Clocks IP is required to implement GTS AXI Streaming IP for PCI Express* to generate the System PLL clock. The clock source of this IP is a 100 MHz PCIe* reference clock.
  • The Reset Release IP holds the control circuit in reset until the device has fully entered user mode. The FPGA asserts the INIT_DONE output to signal that the device is in user mode. The Reset Release IP generates an inverted version of the internal INIT_DONE signal to create the nINIT_DONE output you can use for your design. The nINIT_DONE signal is high until the entire device enters user mode. After nINIT_DONE asserts (low), all logic is in user mode and operates normally.
  • The IOPLL IP generates all the required clock inputs for SSGDMA IP, GTS AXI Streaming IP for PCI Express* , On-chip Memory II IP, and Reset Control module.
  • The Reset Control block manages reset signals of GTS AXI Streaming IP.
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