Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

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ID 823179
Date 1/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide
1. Design Example Description x
1.1. H2D ST to D2H ST Loopback Design Example
1.1. H2D ST to D2H ST Loopback Design Example x
1.1.1. DMA PCIe* Mode Design Example 1.1.2. DMA SoC Mode Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. DMA SoC Mode Example Design 2.3.2. DMA PCIe Mode Example Design
2.3.2. DMA PCIe Mode Example Design x
2.3.2.1. Running Simulation using VCS* MX 2.3.2.2. Running Simulation Using QuestaSim*
2.4. Testbench x
2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
1. Design Example Description
2. Quick Start Guide
3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.01.27 24.3.1 1.1.3
  • Updated the following topics:
    • Design Example Description
    • H2D ST to D2H ST Loopback Design Example
    • DMA PCIe Mode Design Example
    • Generating the Design Example
  • Added new topics:
    • DMA SoC Mode Example Design
    • DMA PCIe Mode Example Design
    • DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
2024.07.08 24.2 1.1.1 Initial release.
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