Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

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ID 823179
Date 1/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide
1. Design Example Description x
1.1. H2D ST to D2H ST Loopback Design Example
1.1. H2D ST to D2H ST Loopback Design Example x
1.1.1. DMA PCIe* Mode Design Example 1.1.2. DMA SoC Mode Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. DMA SoC Mode Example Design 2.3.2. DMA PCIe Mode Example Design
2.3.2. DMA PCIe Mode Example Design x
2.3.2.1. Running Simulation using VCS* MX 2.3.2.2. Running Simulation Using QuestaSim*
2.4. Testbench x
2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
1. Design Example Description
2. Quick Start Guide
3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

2.4. Testbench

The Scalable Scatter-Gather DMA Intel® FPGA IP generates design example and testbench based on chosen configuration.


Section Content
DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench
DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench

Level Two Title