Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

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ID 823179
Date 1/27/2025
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Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide
1. Design Example Description x
1.1. H2D ST to D2H ST Loopback Design Example
1.1. H2D ST to D2H ST Loopback Design Example x
1.1.1. DMA PCIe* Mode Design Example 1.1.2. DMA SoC Mode Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. DMA SoC Mode Example Design 2.3.2. DMA PCIe Mode Example Design
2.3.2. DMA PCIe Mode Example Design x
2.3.2.1. Running Simulation using VCS* MX 2.3.2.2. Running Simulation Using QuestaSim*
2.4. Testbench x
2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
1. Design Example Description
2. Quick Start Guide
3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

2.2. Generating the Design Example

Figure 6. Procedure
  1. In the Quartus® Prime Pro Edition software, create a new project (File > New Project Wizard).
  2. Specify the Directory, Name and Top-Level Entity.
  3. For Family, Device & Board Settings, select Agilex™ 5 (E-series/D-series) and the Target Device for your design.
  4. Click Finish.
  5. In the IP catalog, locate and add the Scalable Scatter-Gather DMA Intel® FPGA IP .
  6. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  7. In the IP Parameter Editor, specify the parameters for your IP variation.
    Note: Only one H2D ST and one D2H ST device port setting is supported for DMA SoC mode H2D ST to D2H ST Single Port Loopback Design Example generation.
    Note: Number of H2D ST and D2H ST device ports must be the same and only one H2D MM device port setting is supported for DMA PCIe Mode Loopback Example Design generation. Optional BAM interface is not supported.
  8. On the Example Design tab, make the following selections:
    1. For Generate Example Design, only the Synthesis and Synthesis & Simulation options are available for DMA PCIe* Mode Design Example. Synthesis, Simulation, and Synthesis & Simulation options are available for DMA SoC Mode Design Example.
    2. Example Design Mode option is automatically populated.
  9. Select Generate Example Design to create a design example you can compile and simulate. When the prompt asks you to specify the directory for your design example, you can accept the default ./intel_ssgdma_0_testbench/ directory or choose another directory.
  10. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the design example.
Figure 7. Example Design Tab
Level Two Title