2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench
This design example demonstrates an H2D ST to D2H ST loopback simulation for DMA SoC mode.
The design example simulation demonstrates the following sequences, which are set up via the Nios® V Subsystem from application software and driver:
- Identifies the number of device ports and corresponding types via IP_PARAM register from the Global CSR during the initialization.
- Performs soft reset sequence on Prefetcher Engine and device ports via the corresponding registers from Global CSR and Device Port CSR during the initialization.
- Enables Prefetcher Engine via CTRL register from the Global CSR.
- Initialize the corresponding H2D ST and D2H ST device ports via the corresponding registers from Device Port CSR.
- Setup corresponding data and responder descriptor buffers for both H2D ST and D2H ST device ports.
- Updates the corresponding Q_INSERT_POINTER registers from Device Port CSR for both H2D ST and D2H ST device ports.
- The application software verifies the data transfer completion via Nios® V Subsystem in the following ways:
- For the H2D ST device port, the Q_EXTRACT_POINTER register is polled to identify if the value updated by hardware matches the Q_INSERT_POINTER value configured by the software.
- For the D2H ST device port, the user-defined interrupt service routine is called upon receiving an interrupt issued from hardware to the Nios® V Subsystem.
- Analyzes the content of the responder descriptors written from hardware.
- Compares the data written back from the D2H ST device port against the data sent over to hardware that outputs at the H2D ST device port.
- Performs soft reset sequence on Prefetcher Engine and device ports via the corresponding registers from Global CSR and Device Port CSR after data transfer completion.
Figure 9. Simulation Waveform for the H2D ST to D2H ST Loopback Design Example
Figure 10. Simulation Output Results
Figure 11. Simulation Output Results (cont.)
Figure 12. Simulation Output Results (cont.)
The following sample output illustrates a successful simulation test run for the Questasim simulator.
# // Questa Intel FPGA Edition-64 # // Version 2023.3 linux_x86_64 Jul 17 2023 # // # // Copyright 1991-2023 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // do run_vsim.do ..... # __________________________________________________________ # INFO: Out of reset status # __________________________________________________________ # __________________________________________________________ # INFO: Interrupt received at Nios V! # __________________________________________________________ # 552726.00 ns ps: Waiting for Prefetch Engine and Device Port soft reset sequence issued from Nios V before data transfer begin # 552726.00 ns ps: Global CSR CTRL is 000100 # INFO: Simple flow for intel ssgdma # INFO: Enabling prefetcher! # INFO: Enable prefetcher: 0, enable 1 # INFO: Dev csr base: 0x800000. total port 2 # 774383.00 ns ps: Global CSR CTRL write request at 200010 with Write Data 00000001 issued by Nios V # 774383.00 ns ps: Waiting for write response send back to Nios V # 814491.00 ns ps: Waiting for H2D_ST Q_INSERT_POINTER write request on Port 0 issued from Nios V # 814491.00 ns ps: H2D_ST Q_INSERT_POINTER Port 0 is 240018 # 814491.00 ns ps: Waiting for D2H_ST Q_INSERT_POINTER write request on Port 0 issued from Nios V # 814491.00 ns ps: D2H_ST Q_INSERT_POINTER Port 0 is 200018 # INFO: ******************************* # INFO: Start transfer for port num 0. # INFO: Fill H2D ST ret 0, length 32 # INFO: Fill H2D ST ret 0, length 32 # INFO: Fill H2D ST ret 0, length 24 # 1348523.00 ns ps: H2D_ST Q_INSERT_POINTER write request at 240018 with Write Data 00000004 issued by Nios V # 1348523.00 ns ps: Waiting for write response send back to Nios V # 1348631.00 ns ps: Waiting for H2D_ST Q_EXTRACT_POINTER read request on Port 0 issued from Nios V # 1348631.00 ns ps: H2D_ST Q_EXTRACT_POINTER Port 0 is 240014 # 1348631.00 ns ps: Waiting for read response send back to Nios V # INFO: H2D_ST update insert ptr ret 0. # 1409919.00 ns ps: H2D_ST Q_EXTRACT_POINTER read request at 240018 issued by Nios V # 1410027.00 ns ps: H2D_ST Q_EXTRACT_POINTER read response returned is 4 # 1410027.00 ns ps: H2D_ST Device Port 0 has completed the data transfer operation up to H2D_ST Q_EXTRACT_POINTER 4! # INFO: H2D_ST insert ptr ret 0, val 4 # INFO: Interrupt D2H_ST before: 0. # INFO: Fill D2H ST ret 0, length 0x58 # 1611742.00 ns ps: D2H_ST Q_INSERT_POINTER write request at 200018 with Write Data 00000004 issued by Nios V # 1611742.00 ns ps: Waiting for write response send back to Nios V # 1611850.00 ns ps: Waiting for D2H_ST Q_EXTRACT_POINTER read request on Port 0 issued from Nios V # 1611850.00 ns ps: D2H_ST Q_EXTRACT_POINTER Port 0 is 200014 # 1611850.00 ns ps: Waiting for read response send back to Nios V # INFO: D2H_ST update insert ptr ret 0. # 1673070.00 ns ps: D2H_ST Q_EXTRACT_POINTER read request at 200018 issued by Nios V # 1673178.00 ns ps: D2H_ST Q_EXTRACT_POINTER read response returned is 4 # 1673178.00 ns ps: D2H_ST Device Port 0 has completed the data transfer operation up to D2H_ST Q_EXTRACT_POINTER 4! # 1673258.00 ns ps: Waiting for Prefetch Engine and Device Port soft reset sequence issued from Nios V after data transfer completion # 1673258.00 ns ps: Global CSR CTRL is 000100 # INFO: D2H_ST insert ptr ret 0, val 4 # INFO: check H2D_ST for complete. # INFO: H2D_ST resp before poll. # INFO: resp format 0x13, Idx 2, length 32, status 0x80 # INFO: resp format 0x13, Idx 3, length 32, status 0x80 # INFO: resp format 0x13, Idx 4, length 24, status 0x81 # INFO: HW Extract pointer after H2D_ST 4, ret 0 # INFO: H2D_ST complete ret 0, last idx 4 # INFO: H2D_ST resp after poll. # INFO: resp format 0x13, Idx 2, length 32, status 0x0 # INFO: resp format 0x13, Idx 3, length 32, status 0x0 # INFO: resp format 0x13, Idx 4, length 24, status 0x1 # INFO: D2H_ST status before interrupt. # INFO: gcsr status: val 0x80000000 # INFO: gcsr irq status: val 0x1 # INFO: type 0, status: ret 0, val 0x90000014 # INFO: interrupt cnt 0, completed desc 0 # INFO: D2H_ST resp before interrupt. # INFO: resp format 0x17, Idx 2, length 32, status 0x80 # INFO: resp format 0x17, Idx 3, length 32, status 0x80 # INFO: resp format 0x17, Idx 4, length 24, status 0x85 # INFO: D2H_ST status after interrupt. # INFO: gcsr status: val 0x0 # INFO: gcsr irq status: val 0x0 # INFO: type 0, status: ret 0, val 0x14 # INFO: interrupt cnt 1, completed desc 3 # INFO: HW Extract pointer after D2H_ST 4, ret 0 # INFO: D2H_ST resp after interrupt. # INFO: resp format 0x17, Idx 2, length 32, status 0x0 # INFO: resp format 0x17, Idx 3, length 32, status 0x0 # INFO: resp format 0x17, Idx 4, length 24, status 0x5 # INFO: Transfered data matches with received data. # INFO: Free resources! # INFO: Reset Ports! # 4166608.00 ns ps: Global CSR CTRL write request at 000100 with Write Data 00000001 issued by Nios V # 4166608.00 ns ps: Waiting for write response send back to Nios V # __________________________________________________________ # INFO: Test PASSED # __________________________________________________________ # PASS # ** Note: $finish : ../../ssgdma_sim_host.sv(111) # Time: 4206719136890 fs Iteration: 5 Region: /ssgdma_ed_top/sim_host_inst/genblk1 # 1 # Break in VlGenerateBlock genblk1 at ../../ssgdma_sim_host.sv line 111