Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

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ID 823179
Date 4/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide
1. Design Example Description x
1.1. H2D ST to D2H ST Loopback Design Example
1.1. H2D ST to D2H ST Loopback Design Example x
1.1.1. DMA PCIe* Mode Design Example 1.1.2. DMA SoC Mode Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. DMA SoC Mode Example Design 2.3.2. DMA PCIe Mode Example Design
2.3.2. DMA PCIe Mode Example Design x
2.3.2.1. Running Simulation using VCS* MX 2.3.2.2. Running Simulation Using QuestaSim* 2.3.2.3. Running Simulation using Xcelium 2.3.2.4. Running Simulation using Riviera-PRO
2.4. Testbench x
2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench x
2.4.2.1. Design Example Testbench
2.7. Running the Design Example x
2.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example 2.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example
2.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example x
2.7.1.1. Building the Software Application Project for Nios® V/m Processor 2.7.1.2. Programming the Example Design into the Development Board
2.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example x
2.7.2.1. Installing the Linux Kernel Driver 2.7.2.2. Running the Loopback Design Example
2.7.2.2. Running the Loopback Design Example x
2.7.2.2.1. Testing H2D ST to D2H ST Loopback 2.7.2.2.2. Testing H2D MM
1. Design Example Description
2. Quick Start Guide
3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

1.1.2. DMA SoC Mode Design Example

Figure 3. H2D ST to D2H ST (Soc Mode) Loopback Design & H2D MM to Onchip Memory

This design example includes the following components:

  • Nios® V Subsystem consists of:
    • AXI4 Lite bridge, which connects the Nios® V processor to the Host CSR AXI4 Lite interface of SSGDMA IP.
    • AXI4 bridge, which connects the Host AXI4 interface of SSGDMA IP to the On-chip Memory II IP, served as Host memory.
    • Nios® V processor
    • JTAG UART IP for application software printout.
  • The generated Scalable Scatter-Gather DMA IP with the parameters you specified. With device-side packet loopback, the Host to Device (H2D) data stream is looped back to the Device to Host (D2H) device port. When you enable the H2D MM port, it connects to On-Chip Memory II IP.
  • The Host AXI IOPLL IP generates all the required clock inputs for SSGDMA IP and Nios® V subsystem.
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