Scalable Scatter-Gather DMA FPGA IP Design Example User Guide

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ID 823179
Date 9/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Product Discontinuance Notification 2. Design Example Description 3. Quick Start Guide 4. Document Revision History for the Scalable Scatter-Gather DMA FPGA IP Design Example User Guide
2. Design Example Description x
2.1. H2D ST to D2H ST Loopback Design Example
2.1. H2D ST to D2H ST Loopback Design Example x
2.1.1. DMA PCIe* Mode Design Example 2.1.2. DMA SoC Mode Design Example
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Testbench 3.5. Compiling the Design Example 3.6. Hardware and Software Requirements 3.7. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. DMA SoC Mode Example Design 3.3.2. DMA PCIe Mode Example Design
3.3.2. DMA PCIe Mode Example Design x
3.3.2.1. Running Simulation using VCS* MX 3.3.2.2. Running Simulation Using QuestaSim* 3.3.2.3. Running Simulation using Xcelium 3.3.2.4. Running Simulation using Riviera-PRO
3.4. Testbench x
3.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 3.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
3.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench x
3.4.2.1. Design Example Testbench
3.7. Running the Design Example x
3.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example 3.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example
3.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example x
3.7.1.1. Building the Software Application Project for Nios® V/m Processor 3.7.1.2. Programming the Example Design into the Development Board
3.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example x
3.7.2.1. Installing the Linux Kernel Driver 3.7.2.2. Running the Loopback Design Example
3.7.2.2. Running the Loopback Design Example x
3.7.2.2.1. Testing H2D ST to D2H ST Loopback 3.7.2.2.2. Testing H2D MM
1. Product Discontinuance Notification
2. Design Example Description
3. Quick Start Guide
4. Document Revision History for the Scalable Scatter-Gather DMA FPGA IP Design Example User Guide

2. Design Example Description

The Scalable Scatter-Gather DMA Intel® FPGA IP provides a design example and simulation testbench that supports compilation and simulation.

The following table lists the terms and definitions used in this document.

Table 1.  Terms and Definitions
Term Definition
API Application Programming Interface
APP2SS Application to PCIe* Subsystem
ATT Address Translation Table
AXI-4 Advanced extensible Interface associated with AMBA version 4.0
AXI-4 Lite AMBA AXI-4 Lite Memory Map Interface
AXI-ST AXI Streaming
BAM Bursting Manager
BAS Bursting Subordinate
CEB Configuration Extension Bus
CSR Control Status Register
D2H Device to Host
DMA Direct Memory Access
DPDK Data Path Development Kit
EOF End of a File (or packet) for streaming
File (or Packet) A group of descriptors defined by SOF and EOF bits of the descriptor for the streaming. At the AXI-ST user interface, a file (or packet) is marked using TUSER.SOF (Optional for SOF) and TLAST (as EOF).
FLR Function Level Reset
H2D Host to Device
HIDX Queue Insert Index (Pointer)
HIP Hard IP
HPS Hard Processor System
IP Intellectual Property
MCDMA Multi-Channel Direct Memory Access
MPS Maximum Payload Size
MRRS Maximum Read Request Size
MSI Message Signaled Interrupt
MSI-X Message Signaled Interrupt - Extended
PBA Pending Bit Array
PCIe* Peripheral Component Interconnect Express ( PCI Express* )
PD Packet Descriptor
PF Physical Function
PMD Poll Mode Driver
QID Queue Identification
QOS Quality of Service
SoC System on Chip
SOF Start of a File (or packet) for streaming
SR-IOV Single Root I/O Virtualization
SS Subsystem
SS2APP PCIe* Subsystem to Application
TIDX Queue Extract Index (Pointer)
TLP Transaction Layer Protocol
VF Virtual Function

The following table presents an overview of the design example supported by the Scalable Scatter-Gather DMA Intel® FPGA IP:

Table 2.  Design Example Overview
IP Mode Design Example Mode Compilation Simulation Hardware
DMA PCIe* Mode Multiport H2D-ST to D2H-ST Loopback & H2D MM to Onchip Memory Supported Supported Supported (for 128-bit data width design variant only)
DMA SoC Mode Multiport H2D-ST to D2H-ST Loopback & H2D-MM to Onchip memory Supported Supported Supported

You can generate the design example from the Example Design tab of the Scalable Scatter-Gather DMA IP Parameter Editor.


Section Content
H2D ST to D2H ST Loopback Design Example

Level Two Title