AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
ID
817911
Date
4/07/2025
Public
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5.3.1. PCIe AXI-ST TX Interface (ss_tx_st)
5.3.2. PCIe AXI-ST RX Interface (ss_rx_st)
5.3.3. Control and Status Register Interface (ss_csr_lite)
5.3.4. Flow Control Credit Interface
5.3.5. Configuration Intercept Interface (CII)
5.3.6. Completion Timeout Interface (ss_cplto)
5.3.7. Function Level Reset Interface
5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.4.1. H2D AXI-ST Source (h2d_st_initatr)
5.4.2. D2H AXI-ST Sink (d2h_st_respndr)
5.4.3. H2D/D2H AXI-MM Master
5.4.4. BAM AXI-MM Master (bam_mm_initatr)
5.4.5. BAS AXI-MM Slave (bas_mm_respndr)
5.4.6. PIO AXI-Lite Master (pio_lite_initiatr)
5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite)
5.4.8. User Event MSI-X (user_msix)
5.4.9. User Event MSI (user_msi)
5.4.10. User Function Level Reset (user_flr)
5.4.11. User Configuration Intercept Interface - EP Only
5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
5.4.8. User Event MSI-X (user_msix)
User logic can request the DMA engine to send an event interrupt for a queue associated with a PF/VF.
Interface clock : axi_lite_clk
Signal Name | Direction | Description |
---|---|---|
user_event_msix_tvalid | Input | The valid signal qualifies valid data on any cycle with data transfer. |
user_event_msix_tready | Output | On interfaces supporting backpressure, the sink asserts ready to mark the cycles where transfers may take place. |
user_event_msix_tdata[15:0] | Input |
{msix_queue_dir, rsvd[3:0], msix_queue_num_i[10:0]}
Note: msix_queue_dir denotes DMA direction.
|