AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

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ID 817911
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Functional Description 4. Parameters 5. Interfaces 6. Designing with the IP Core 7. Known Issues 8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
1. About This Document x
1.1. Intended Audience 1.2. Conventions 1.3. Terms and Acronyms 1.4. Related Information
2. Introduction x
2.1. Overview 2.2. IP Features 2.3. Device Family Support 2.4. IP and Design Example Support 2.5. Recommended Speed Grade 2.6. Resource Utilization 2.7. Release Information
2.2. IP Features x
2.2.1. Root Port Mode Features 2.2.2. Endpoint Mode Features 2.2.3. Design Example Support
4. Parameters x
4.1. IP Settings 4.2. Design Examples
4.1. IP Settings x
4.1.1. PCIe Settings
4.1.1. PCIe Settings x
4.1.1.1. MCDMA Settings 4.1.1.2. PCI Express / PCI Capabilities 4.1.1.3. Base Address Registers
4.1.1.1. MCDMA Settings x
4.1.1.1.1. Multichannel DMA Mode 4.1.1.1.2. Bursting Master Mode 4.1.1.1.3. Bursting Slave Mode 4.1.1.1.4. BAM+BAS Mode 4.1.1.1.5. BAM+MCDMA Mode 4.1.1.1.6. BAM+BAS+MCDMA Mode
4.1.1.2. PCI Express / PCI Capabilities x
4.1.1.2.1. PCIe Device 4.1.1.2.2. PCIe MSI-X
4.1.1.2.2. PCIe MSI-X x
4.1.1.2.2.1. PCIe PF MSI-X 4.1.1.2.2.2. PCIe VF MSI-X
4.2. Design Examples x
4.2.1. Aligning AXI MCDMA IP Settings with AXI Streaming IP for PCI Express
5. Interfaces x
5.1. System Block Diagram 5.2. Clocks and Resets 5.3. PCIe IP-facing Interfaces 5.4. User-facing Interfaces
5.3. PCIe IP-facing Interfaces x
5.3.1. PCIe AXI-ST TX Interface (ss_tx_st) 5.3.2. PCIe AXI-ST RX Interface (ss_rx_st) 5.3.3. Control and Status Register Interface (ss_csr_lite) 5.3.4. Flow Control Credit Interface 5.3.5. Configuration Intercept Interface (CII) 5.3.6. Completion Timeout Interface (ss_cplto) 5.3.7. Function Level Reset Interface 5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.3.4. Flow Control Credit Interface x
5.3.4.1. Transmit Flow Credit Interface (ss_txcrdt) 5.3.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)
5.3.5. Configuration Intercept Interface (CII) x
5.3.5.1. Configuration Intercept Request Interface (ss_cii_req) 5.3.5.2. Configuration Intercept Response Interface (ss_cii_resp)
5.3.7. Function Level Reset Interface x
5.3.7.1. FLR Received Interface (ss_flrrcvd) 5.3.7.2. FLR Completion Interface (ss_flrcmpl)
5.4. User-facing Interfaces x
5.4.1. H2D AXI-ST Source (h2d_st_initatr) 5.4.2. D2H AXI-ST Sink (d2h_st_respndr) 5.4.3. H2D/D2H AXI-MM Master 5.4.4. BAM AXI-MM Master (bam_mm_initatr) 5.4.5. BAS AXI-MM Slave (bas_mm_respndr) 5.4.6. PIO AXI-Lite Master (pio_lite_initiatr) 5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite) 5.4.8. User Event MSI-X (user_msix) 5.4.9. User Event MSI (user_msi) 5.4.10. User Function Level Reset (user_flr) 5.4.11. User Configuration Intercept Interface - EP Only 5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
5.4.3. H2D/D2H AXI-MM Master x
5.4.3.1. AXI-MM Write (H2D) 5.4.3.2. AXI-MM Read Channel (D2H)
5.4.11. User Configuration Intercept Interface - EP Only x
5.4.11.1. User Configuration Intercept Request Interface (user_cii_req) 5.4.11.2. User Configuration Intercept Response Interface (user_cii_resp)
6. Designing with the IP Core x
6.1. Generating the IP Core 6.2. IP Core Generation Output 6.3. Simulating the IP Core 6.4. Quick Start Guide
6.4. Quick Start Guide x
6.4.1. Functional Description 6.4.2. Generating the Design Example 6.4.3. Simulating the Design Example 6.4.4. Testing the Design Example
1. About This Document
2. Introduction
3. Functional Description
4. Parameters
5. Interfaces
6. Designing with the IP Core
7. Known Issues
8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

4.1.1.1.1. Multichannel DMA Mode

Figure 3. Multichannel DMA Mode Parameters
Table 11.  Multichannel DMA Mode Parameters
Parameter Value Default Value Description
BAR2 Address Width

128 Bytes – 7 bits

. . .

8 EBytes – 63 bits

4 Mbytes – 22 bits

Sets the BAR2 size used for PIO functionality.

Note: This parameter is available only in Multichannel DMA user mode.
User Mode

Multichannel DMA

Bursting Master

Bursting Slave

BAM+BAS

BAM+MCDMA

BAM+BAS+MCDMA

Multichannel DMA
This parameter allows you to configure the mode of operation for the user application:
  • Bursting Master (BAM) and Bursting Slave (BAS) offer bursting AXI-MM capabilities without DMA functionality
User Interface

AXI-S

AXI-MM

AXI-S

Sets the type of DMA user interface.

You can select either the AXI Stream or AXI Memory-Mapped interface for DMA.
Enable User-FLR On / Off Off

Select to enable User FLR interface which allows passing of FLR signals to the user side application.

Note: User FLR is not supported in Bursting Master, Bursting Slave, and BAM+BAS modes.
Enable User-MSIX On / Off Off

User MSI-X interface enables the user application to initiate interrupts through the MCDMA IP.

Note: User MSI-X is not supported in Bursting Master, Bursting Slave, and BAM+BAS modes.
Enable Metadata On / Off Off

Enables or disables 8-byte metadata.

Metadata is the 8-byte user application data that is transferred to and from the device via the DEST address field (for H2D DMA) and SRC address field (for D2H DMA) in the AXI Streaming mode.

Note: Metadata is not supported in Bursting Master, Bursting Slave, and BAM+BAS modes.
Enable Configuration Intercept Interface On / Off Off

Select to enable user configuration intercept interface.
Enable HIP Reconfiguration Interface On / Off Off

Select to enable Hard IP reconfiguration interface.
Enable address byte aligned transfer Off Off

This option is not supported in the current release.

Enable 10-bit tag support interface On On

Enables 10-bit tag support interface
Enable Completion Re-order On On

Enables completion re-order
Enable Completion Timeout Interface On On

Enables completion timeout interface
D2H Prefetch channels 8

16

32

64

128

256

512

8 Sets the number of D2H prefetch channels for the AXI-S interface type. IP Parameter Editor automatically selects the value based on the DMA channel count.
Maximum Descriptor Fetch 16

32

64

16 Sets the maximum descriptors that are fetched per D2H prefetch channel. Applicable to the AXI-S interface type.
Level Two Title