AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

ID 817911
Date 4/07/2025
Public

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2.2.3. Design Example Support

The table below lists the AXI MCDMA design examples available in the AXI MCDMA IP Parameter Editor under the Example Designs tab. Based on the IP parameter settings, such as User Mode and User Interface, you can select a design example, compile it, and perform a hardware test.

Note: Design example simulation may be supported in a future release.
Table 3.  AXI MCDMA Endpoint Design Example Support
User Mode DMA User Interface Available Design Example
Multichannel DMA

BAM + MCDMA

BAM + BAS + MCDMA

AXI Streaming AXI-S Device-side Packet Loopback
Multichannel DMA

Bam + MCDMA

BAM + BAS + MCDMA

AXI Memory-Mapped AXI-MM DMA
BAM + BAS n/a AXI-MM Traffic Generator/Checker
Bursting Master (BAM) n/a AXI-MM BAM EP Memory