AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
ID
817911
Date
4/07/2025
Public
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5.3.1. PCIe AXI-ST TX Interface (ss_tx_st)
5.3.2. PCIe AXI-ST RX Interface (ss_rx_st)
5.3.3. Control and Status Register Interface (ss_csr_lite)
5.3.4. Flow Control Credit Interface
5.3.5. Configuration Intercept Interface (CII)
5.3.6. Completion Timeout Interface (ss_cplto)
5.3.7. Function Level Reset Interface
5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.4.1. H2D AXI-ST Source (h2d_st_initatr)
5.4.2. D2H AXI-ST Sink (d2h_st_respndr)
5.4.3. H2D/D2H AXI-MM Master
5.4.4. BAM AXI-MM Master (bam_mm_initatr)
5.4.5. BAS AXI-MM Slave (bas_mm_respndr)
5.4.6. PIO AXI-Lite Master (pio_lite_initiatr)
5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite)
5.4.8. User Event MSI-X (user_msix)
5.4.9. User Event MSI (user_msi)
5.4.10. User Function Level Reset (user_flr)
5.4.11. User Configuration Intercept Interface - EP Only
5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
2.2.3. Design Example Support
The table below lists the AXI MCDMA design examples available in the AXI MCDMA IP Parameter Editor under the Example Designs tab. Based on the IP parameter settings, such as User Mode and User Interface, you can select a design example, compile it, and perform a hardware test.
Note: Design example simulation may be supported in a future release.
User Mode | DMA User Interface | Available Design Example |
---|---|---|
Multichannel DMA BAM + MCDMA BAM + BAS + MCDMA |
AXI Streaming | AXI-S Device-side Packet Loopback |
Multichannel DMA Bam + MCDMA BAM + BAS + MCDMA |
AXI Memory-Mapped | AXI-MM DMA |
BAM + BAS | n/a | AXI-MM Traffic Generator/Checker |
Bursting Master (BAM) | n/a | AXI-MM BAM EP Memory |