AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

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ID 817911
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Functional Description 4. Parameters 5. Interfaces 6. Designing with the IP Core 7. Known Issues 8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
1. About This Document x
1.1. Intended Audience 1.2. Conventions 1.3. Terms and Acronyms 1.4. Related Information
2. Introduction x
2.1. Overview 2.2. IP Features 2.3. Device Family Support 2.4. IP and Design Example Support 2.5. Recommended Speed Grade 2.6. Resource Utilization 2.7. Release Information
2.2. IP Features x
2.2.1. Root Port Mode Features 2.2.2. Endpoint Mode Features 2.2.3. Design Example Support
4. Parameters x
4.1. IP Settings 4.2. Design Examples
4.1. IP Settings x
4.1.1. PCIe Settings
4.1.1. PCIe Settings x
4.1.1.1. MCDMA Settings 4.1.1.2. PCI Express / PCI Capabilities 4.1.1.3. Base Address Registers
4.1.1.1. MCDMA Settings x
4.1.1.1.1. Multichannel DMA Mode 4.1.1.1.2. Bursting Master Mode 4.1.1.1.3. Bursting Slave Mode 4.1.1.1.4. BAM+BAS Mode 4.1.1.1.5. BAM+MCDMA Mode 4.1.1.1.6. BAM+BAS+MCDMA Mode
4.1.1.2. PCI Express / PCI Capabilities x
4.1.1.2.1. PCIe Device 4.1.1.2.2. PCIe MSI-X
4.1.1.2.2. PCIe MSI-X x
4.1.1.2.2.1. PCIe PF MSI-X 4.1.1.2.2.2. PCIe VF MSI-X
4.2. Design Examples x
4.2.1. Aligning AXI MCDMA IP Settings with AXI Streaming IP for PCI Express
5. Interfaces x
5.1. System Block Diagram 5.2. Clocks and Resets 5.3. PCIe IP-facing Interfaces 5.4. User-facing Interfaces
5.3. PCIe IP-facing Interfaces x
5.3.1. PCIe AXI-ST TX Interface (ss_tx_st) 5.3.2. PCIe AXI-ST RX Interface (ss_rx_st) 5.3.3. Control and Status Register Interface (ss_csr_lite) 5.3.4. Flow Control Credit Interface 5.3.5. Configuration Intercept Interface (CII) 5.3.6. Completion Timeout Interface (ss_cplto) 5.3.7. Function Level Reset Interface 5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.3.4. Flow Control Credit Interface x
5.3.4.1. Transmit Flow Credit Interface (ss_txcrdt) 5.3.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)
5.3.5. Configuration Intercept Interface (CII) x
5.3.5.1. Configuration Intercept Request Interface (ss_cii_req) 5.3.5.2. Configuration Intercept Response Interface (ss_cii_resp)
5.3.7. Function Level Reset Interface x
5.3.7.1. FLR Received Interface (ss_flrrcvd) 5.3.7.2. FLR Completion Interface (ss_flrcmpl)
5.4. User-facing Interfaces x
5.4.1. H2D AXI-ST Source (h2d_st_initatr) 5.4.2. D2H AXI-ST Sink (d2h_st_respndr) 5.4.3. H2D/D2H AXI-MM Master 5.4.4. BAM AXI-MM Master (bam_mm_initatr) 5.4.5. BAS AXI-MM Slave (bas_mm_respndr) 5.4.6. PIO AXI-Lite Master (pio_lite_initiatr) 5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite) 5.4.8. User Event MSI-X (user_msix) 5.4.9. User Event MSI (user_msi) 5.4.10. User Function Level Reset (user_flr) 5.4.11. User Configuration Intercept Interface - EP Only 5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
5.4.3. H2D/D2H AXI-MM Master x
5.4.3.1. AXI-MM Write (H2D) 5.4.3.2. AXI-MM Read Channel (D2H)
5.4.11. User Configuration Intercept Interface - EP Only x
5.4.11.1. User Configuration Intercept Request Interface (user_cii_req) 5.4.11.2. User Configuration Intercept Response Interface (user_cii_resp)
6. Designing with the IP Core x
6.1. Generating the IP Core 6.2. IP Core Generation Output 6.3. Simulating the IP Core 6.4. Quick Start Guide
6.4. Quick Start Guide x
6.4.1. Functional Description 6.4.2. Generating the Design Example 6.4.3. Simulating the Design Example 6.4.4. Testing the Design Example
1. About This Document
2. Introduction
3. Functional Description
4. Parameters
5. Interfaces
6. Designing with the IP Core
7. Known Issues
8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

5.4.3.1. AXI-MM Write (H2D)

The AXI-MM Write channel is used to transfer H2D DMA data to the external AXI-MM responder. This interface supports a write width of up to 1024 bits, enabling a maximum of 512 bytes per AXI-MM transaction.

The ReadyLatency of this port is enabled and set as follows:

  • 64 for a 128-bit data width
  • 32 for a 256-bit data width
  • 16 for a 512-bit data width
  • 8 for a 1024-bit data width

This ReadyLatency allows the master to continue transferring data even after the ready signal has been de-asserted.

Table 44.  AXI-MM Write Channel (H2D)
Signal Name Direction Description
Write Address Channel
dma_axi_mm_awvalid Output Write address valid. This signal indicates that the channel is signaling valid write address and control information.
dma_axi_mm_awready Input Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
dma_axi_mm_awid[3:0] Output Transaction ID for the Write channel. Depends on the number of outstanding requests (default is 4 outstanding requests).
dma_axi_mm_awaddr[63:0] Output Write address. The write address gives the address of the first transfer in a write burst transaction.
dma_axi_mm_awlen[7:0] Output Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
dma_axi_mm_awsize[2:0] Output Burst size. This signal indicates the size of each transfer in the burst.
dma_axi_mm_awburst[1:0] Output Burst type. The burst type, along with the burst size information, determines how the address is calculated for each transfer within the burst. AXI MCDMA supports only INCR burst type.
dma_axi_mm_awprot[2:0] Output

Protection type. This signal indicates the privilege and

security level of the transaction, and whether the

transaction is a data access or an instruction access. (not used)
dma_axi_mm_awlock Output Lock type. Tied to '0'.
Write Data Channel
dma_axi_mm_wvalid Output Write valid.
dma_axi_mm_wready Input Write ready. Indicates the receiver can accept write data.
dma_axi_mm_wdata

x16: [1023:0]

x8: [511:0]

x4: [255:0]

Output Write data. The data width depends on the PCIe mode configuration.
dma_axi_mm_wstrb

x16: [127:0]

x8: [63:0]

x4: [31:0]

Output Write strobes. Signal width: data width / 8.
dma_axi_mm_wlast Output Write last.
Write Response Channel
dma_axi_mm_bvalid Input Write response valid
dma_axi_mm_bready Output Write response ready
dma_axi_mm_bid[3:0] Input Transaction ID for the Write channel.
dma_axi_mm_bresp[1:0] Input Write response.
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