AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

ID 817911
Date 4/07/2025
Public

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Document Table of Contents

2.4. IP and Design Example Support

Table 5.  Endpoint Mode
PCIe Mode IP Support Design Example Support Note
Gen5/4/3 1x16 Yes Yes To generate the 1x16 IP or design example:
  • Select IP PCIe Mode: 1x16.
  • Select IP Data Width.
  • Select the design example PCIe Mode in the PCIe Settings tab of the Example Designs tab: 1x16.
Gen5/4/3 1x8 Yes No To generate the 1x8 IP:
  • Create a quartus.ini file with content: ini_guard=on.
  • Select IP PCIe Mode: 1x8.
  • Select IP Data Width.
  • Select the design example PCIe Mode in the PCIe Settings tab of the Example Designs tab: x8.
Gen5/4/3 1x4 Yes No To generate the 1x4 IP:
  • Create a quartus.ini file with content: ini_guard=on.
  • Select IP PCIe Mode: 1x4.
  • Select IP Data Width.
  • Select design example PCIe Mode: x4.
Table 6.  Root Port Mode
PCIe Mode IP Support Design Example Support Note
Gen5/4/3 1x16 Yes No To generate the 1x16 IP:
  • Select IP PCIe Mode: 1x16.
  • Select IP Data Width.
  • Select design example PCIe Mode: 1x16.
Gen5/4/3 1x8 Yes No To generate the 1x8 IP:
  • Create a quartus.ini file with the content: ini_guard=on.
  • Select IP PCIe Mode: 1x8.
  • Select IP Data Width.
  • Select design example PCIe Mode: x8.
Gen5/4/3 1x4 Yes No To generate the 1x4 IP:
  • Create a quartus.ini file with the content: ini_guard=on.
  • Select IP PCIe Mode: 1x4.
  • Select IP Data Width.
  • Select design example PCIe Mode: x4.
Note: For 2x8, 2x4, and 4x4, you can generate the IP as 1x8 or 1x4 and use multiple instances with the appropriate AXI Streaming IP to build design examples.