AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
ID
817911
Date
4/07/2025
Public
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5.3.1. PCIe AXI-ST TX Interface (ss_tx_st)
5.3.2. PCIe AXI-ST RX Interface (ss_rx_st)
5.3.3. Control and Status Register Interface (ss_csr_lite)
5.3.4. Flow Control Credit Interface
5.3.5. Configuration Intercept Interface (CII)
5.3.6. Completion Timeout Interface (ss_cplto)
5.3.7. Function Level Reset Interface
5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.4.1. H2D AXI-ST Source (h2d_st_initatr)
5.4.2. D2H AXI-ST Sink (d2h_st_respndr)
5.4.3. H2D/D2H AXI-MM Master
5.4.4. BAM AXI-MM Master (bam_mm_initatr)
5.4.5. BAS AXI-MM Slave (bas_mm_respndr)
5.4.6. PIO AXI-Lite Master (pio_lite_initiatr)
5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite)
5.4.8. User Event MSI-X (user_msix)
5.4.9. User Event MSI (user_msi)
5.4.10. User Function Level Reset (user_flr)
5.4.11. User Configuration Intercept Interface - EP Only
5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
2.4. IP and Design Example Support
PCIe Mode | IP Support | Design Example Support | Note |
---|---|---|---|
Gen5/4/3 1x16 | Yes | Yes | To generate the 1x16 IP or design example:
|
Gen5/4/3 1x8 | Yes | No | To generate the 1x8 IP:
|
Gen5/4/3 1x4 | Yes | No | To generate the 1x4 IP:
|
PCIe Mode | IP Support | Design Example Support | Note |
---|---|---|---|
Gen5/4/3 1x16 | Yes | No | To generate the 1x16 IP:
|
Gen5/4/3 1x8 | Yes | No | To generate the 1x8 IP:
|
Gen5/4/3 1x4 | Yes | No | To generate the 1x4 IP:
|
Note: For 2x8, 2x4, and 4x4, you can generate the IP as 1x8 or 1x4 and use multiple instances with the appropriate AXI Streaming IP to build design examples.