AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

ID 817911
Date 4/07/2025
Public

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5.3.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)

The RX flow control interface provides information on the MCDMA’s available RX buffer space for Posted, Non-Posted and Completion transactions to the AXI PCIe IP. It reports the space available in number of credits as specified by the PCIe Specification.

Table 35.  Receive Flow Credit Interface
Signal Name Direction Description
app_ss_st_rxcrdt_tvalid Output Indicates that the credit information on tdata is valid.
app_ss_st_rxcrdt_tdata[18:0] Output

Carries the credit limit information and type of credit.

[15:0]: Credit Limit Value
  • All zero indicates infinite credit for P, NP, CPL
[18:16]: Credit Type
  • 3'b000 - Posted Header Credit
  • 3'b001 - Non-Posted Header Credit
  • 3'b010 - Completion Header Credit
  • 3'b011 – Reserved
  • 3'b100 – Posted Data Credit
  • 3'b101 - Non-Posted Data Credit
  • 3'b110 - Completion Data Credit
  • 3'b111 - Reserved