Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs

ID 813968
Date 4/25/2025
Public

Visible to Intel only — GUID: hyj1690831447467

Ixiasoft

Document Table of Contents

3.3.3.2. Pipeline Registers for Tensor Floating-point Mode

There are three columns of pipeline registers for tensor floating-point mode. These pipeline registers are not bypassable.