Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: lat1690718775227
Ixiasoft
Visible to Intel only — GUID: lat1690718775227
Ixiasoft
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic
The Agilex™ 5 variable precision DSP block supports accumulator and adder up to 64 bits for fixed-point arithmetic.
The following signals can dynamically control the function of the accumulator and the chainout adder:
- NEGATE
- LOADCONST
- ACCUMULATE
The accumulator and chainout adder features are not available in two fixed-point arithmetic independent 18 x 19 modes and INT16 complex multiplication mode.
Function | Description | NEGATE | LOADCONST | ACCUMULATE |
---|---|---|---|---|
Zeroing | Disables the accumulator. | 0 | 0 | 0 |
Preload | The result is always added to the preload value. Only one bit of the 64-bit preload value can be "1". You can use this function to round the DSP result to any position of the 64-bit result. | 0 | 1 | 0 |
Accumulation | Adds the current result to the previous accumulate result. | 0 | X | 1 |
Decimation + Accumulation | This function takes the current result, converts it into two’s complement, and adds it to the previous result. | 1 | X | 1 |
Decimation + Chainout Adder | This function takes the current result, converts it into two’s complement, and adds it to the output of previous DSP block. | 1 | 0 | 0 |