Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs

ID 813968
Date 4/25/2025
Public

Visible to Intel only — GUID: qsj1690741093017

Ixiasoft

Document Table of Contents

8.3. Parameters

You can customize the Multiply Adder FPGA IP core by specifying the parameters using the parameter editor in the Quartus® Prime software.