Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: xoj1549880793424
Ixiasoft
Visible to Intel only — GUID: xoj1549880793424
Ixiasoft
4.1.5. Chainout Adder/Accumulator Feature
When the chainout cascade is available, the chainout adder/accumulator can be enabled by using the ACCUMULATE and LOADCONST dynamic inputs and the “use_chainadder” and “load_const_value” parameters.
The chainout adder path is enabled by the “use_chainadder” parameter. A full 64-bit chainin port must be connected to the chainout port in previous MAC when “use_chainadder” is set to true. All MACs being chained must use m18x18_systolic operation mode.
The accumulator path is dynamically controlled by the ACCUMULATE input. To disable the accumulator, tie ACCUMULATE to ground, otherwise you must enable the output register.
You can enable the second stage accumulator using the “enable_double_accum” parameter. When it is enabled, the double accumulator register control is not exposed to the user and it always shares the same clock enable as the "output_clken" parameter setting.
The chainout adder/accumulator feature is applicable to m18x18_sumof2, m18x18_plus36, m18x18_systolic, m27x27 and m9x9_sumof6. The chainout adder is not available in m18x18_full mode and complex_mult mode.
When the accumulator is disabled or in the loading stage, a preset constant can be added to the result. It is dynamically controlled by the LOADCONST input. The constant can be 2N (N < 64), and N is set by the “load_const_value” parameter. This operation can be used as biased rounding.
The following figure shows a fully-enabled chainout adder and accumulator. When both ACCUMULATE and LOADCONST are enabled at the same time, the accumulator path is selected instead of the "load_const_value".