General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public
Document Table of Contents

2.2.3. Programmable I/O Element Features for the HSIO Bank

Table 4.  Programmable Slew Rate, De-Emphasis, Receiver Equalization Calibration, and I/O DelayThis table lists the I/O standards that the feature supports and the available settings for each I/O standard.
I/O Standard Slew Rate Control De-Emphasis Receiver Equalization Calibration I/O Delay5
  • 1.3 V LVCMOS
  • 1.2 V LVCMOS
  • 1.1 V LVCMOS
  • 1.05 V LVCMOS
  • 1.0 V LVCMOS
  • Fastest
  • Fast
  • Medium (Default)
  • Slow
Off Refer to the device data sheet
  • SSTL-12 / Differential SSTL-12
  • HSTL-12 / Differential HSTL-12
  • HSUL-12 / Differential HSUL-12
  • Off (Default)
  • Low LP
  • Medium LP
  • High LP
  • Low CZ
  • Medium CZ
  • High CZ
  • Off (Default)
  • Small
  • Medium
  • Large
  • POD12 / Differential POD12
  • POD11 / Differential POD11
  • LVSTL11 / Differential LVSTL11
  • LVSTL105 / Differential LVSTL105
  • LVSTL700 / Differential LVSTL700
  • SLVS-400
  • DPHY
  • Fastest (Default)
  • Fast
  • Medium
  • Slow
True Differential Signaling
Table 5.  Programmable Weak Pull-Up ResistorThis table lists the I/O standard that the features support and the available settings.
I/O Standard Weak Pull-Up Resistor
  • 1.3 V LVCMOS
  • 1.2 V LVCMOS
  • 1.1 V LVCMOS
  • 1.05 V LVCMOS
  • 1.0 V LVCMOS
  • Off (Default)
  • On
Table 6.  Programmable Pre-Emphasis and Differential Output VoltageThis table lists the I/O standard that the features support and the available settings.
I/O Standard Pre-Emphasis Differential Output Voltage
True Differential Signaling
  • Off
  • On (Default)
  • Low
  • Medium low
  • Medium high (Default)
  • High
5 Delay chain is not supported in the LVDS SERDES receiver mode.