General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public
Document Table of Contents

8.5. Decision Feedback Equalization

Compared to CTLE, DFE has improved signal-to-noise ratio. The DFE amplifies only the power of the high frequency components of the signal without amplifying the power of the noise content.

The DFE minimizes post-cursor inter-symbol interference by adding or subtracting weighted versions of the previously received bits from the current bit. The DFE circuit stores delayed versions of the data. The stored bit is multiplied by a coefficient, with programmable polarity, and then summed up with the incoming signal.

Supporting four fixed taps, the DFE can remove the inter-symbol interference from the next four bits beginning from the current bit.