Visible to Intel only — GUID: xoy1662556699079
Ixiasoft
Visible to Intel only — GUID: xoy1662556699079
Ixiasoft
7.7.3.2. DDIO Input Register
Command | Command Example | Description |
---|---|---|
create_clock | create_clock -name virtual_clock -period "200 MHz" create_clock -name ddio_in_clk -period "200 MHz" ddio_in_clk |
Create clock setting for the virtual clock and the DDIO clock. |
set_input_delay | set_input_delay -clock virtual_clock 0.25 ddio_in_data set_input_delay -add_delay -clock_fall -clock virtual_clock 0.25 ddio_in_data |
Instruct the Timing Analyzer to analyze the positive clock edge and the negative clock edge of the transfer. Note the -add_delay in the second set_input_delay command. |
set_false_path | set_false_path -fall_from virtual_clock -rise_to ddio_in_clk set_false_path -rise_from virtual_clock -fall_to ddio_in_clk |
Instruct the Timing Analyzer to ignore the positive clock edge to the negative edge triggered register, and the negative clock edge to the positive edge triggered register. |