General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public
Document Table of Contents

7.5.1. GPIO Intel® FPGA IP Data Paths

Figure 38.  High-Level View of Single-Ended I/O


Table 60.   GPIO IP Data Path Modes
Data Path Register Mode
Bypass Simple Register DDIO
Input Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). The DDIO operates as a simple register. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. The DDIO operates as a regular DDIO.
Output Data goes from the core straight to the delay element, bypassing all DDIOs.
Bidirectional The output buffer drives both an output pin and an input buffer. The DDIO operates as a simple register. The output buffer drives both an output pin and an input buffer. The DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops.

If you use asynchronous clear and preset signals, all DDIOs share these same signals.