General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
ID
813934
Date
8/04/2025
Public
1. Agilex™ 5 General-Purpose I/O Overview
2. Agilex™ 5 HSIO Banks
3. Agilex™ 5 HVIO Banks
4. Agilex™ 5 HPS I/O Banks
5. Agilex™ 5 SDM I/O Banks
6. Agilex™ 5 I/O Troubleshooting Guidelines
7. GPIO FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. HSIO Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. Clock Restrictions for GPIO Interfaces
2.5.12. SDM Shared I/O Requirements
2.5.13. Unused Pins
2.5.14. VCCIO_PIO Supply for Unused HSIO Banks
2.5.15. HSIO Pins During Power Sequencing
2.5.16. Drive Strength Requirement for HSIO Input Pins
2.5.17. Maximum DC Current Restrictions
2.5.18. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.19. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.20. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.21. Implementing a Pseudo Open Drain
2.5.22. Allowed Duration for Using RT OCT
2.5.23. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.24. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
2.2.3.3. Guidelines: Programmable De-Emphasis
- The de-emphasis effect reduces eye height. If you use a non-default de-emphasis setting, perform an IBIS or HSPICE simulation to estimate the electrical performance of the I/O buffer.
- To get the optimal setting for your design, start the simulation with the lowest de-emphasis setting. From there, fine-tune the setting until you get the best signal integrity.
- If you use the compensated slew rate setting, de-emphasis is supported only in the following modes:
- External memory interface
- PHY Lite
- MIPI* D-PHY*
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