General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 8/04/2025
Public
Document Table of Contents

9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2025.08.04 25.1.1
  • Added new topic—Clock Restrictions for GPIO Interfaces.
  • Updated Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank.
  • Updated the note about VREF Sources and Input Standards Grouping.
  • Updated Unused Pins.
  • Removed support for Decision Feedback Equalization.
  • Added a note about package B23B in HVIO Bank Overview.
  • Updated Table: GPIO FPGA IP Current Release Information.
  • Updated the following IP names:
    • "Hard Processor System Intel Agilex 5 FPGA IP" to "Hard Processor System FPGA IP"
    • "GPIO Intel® FPGA IP" to "GPIO FPGA IP".
  • Updated the note about the MIPI* D-PHY* interface in Table: Types of I/O Interfaces.
  • Added the LVDS pin counts to the following figures:
    • Figure: Package Options, Migrations, and I/O Pins—D-Series
    • Figure: Package Options, Migrations, and I/O Pins—E-Series
  • Updated the note about the Variable Pitch BGA (VPBGA) packaging throughout the document.
  • Updated for latest branding standards.
2025.02.17 24.3 Updated the guideline about the RZQ pin placement in RZQ Pin Requirement.
2024.10.07 24.3
  • Updated the following figures:
    • Figure: Package Options, Migrations, and I/O Pins—D-Series
    • Figure: Package Options, Migrations, and I/O Pins—E-Series
  • Updated the guidelines in VCCIO_PIO Supply for Unused HSIO Banks.
  • Removed information about True Differential Signaling from Group 4 and 5 in Table: Input Standards Groups Per I/O Lane.
  • Removed topic Guidelines: Programmable Receiver Equalization Calibration.
  • Clarified that VCCIO_PIO refers to the real-time onboard voltage supply in HSIO Buffer Behavior.
  • Updated HVIO Buffer Behavior:
    • Updated the HVIO pins guideline for the Not turned on pin state.
    • Clarified that VCCIO_HVIO refers to the real-time onboard voltage supply.
  • Added the topic about assigning pin I/O standards in the Quartus® Prime pin planner for the HVIO banks.
  • Updated the guidelines for I/O pins in HVIO banks during power sequencing.
  • Clarified that VCCIO_HPS refers to the real-time onboard voltage supply in HPS I/O Buffer Behavior.
  • Clarified that VCCIO_SDM refers to the real-time onboard voltage supply in SDM I/O Buffer Behavior.
  • Added information about delay calculations in Delay Elements.
2024.04.05 24.1 Initial release.