MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 4/26/2024
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Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interface Overview 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resource Utilization 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interface Overview x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PHY Protocol Interface (PPI) Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Streaming Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PHY-Protocol Interface (PPI) Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for Intel® FPGA IP Cores and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PHY Protocol Interface (PPI) Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interface Overview
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resource Utilization

The following table shows the typical device resource utilization for selected configurations using the Quartus® Prime Pro Edition software version 24.1. The number of ALMs and logic registers are rounded up to the nearest 50. The number stated for M20K memory blocks includes no rounding.
Table 3.  CSI-2 Receiver Performance and Resource Utilization
Configuration ALMs M20K Memory Blocks Logic Registers
Data Lanes PPI Bus Width Pixel-in-Parallel Buffer Depth Data Type Supported
1 1 1 RAW8 4096 1900 2 4300
1 4 1 RAW8 4096 1950 2 4450
1 1 4 RAW8 4096 2900 8 6000
1 4 4 RAW8 4096 3050 8 6500
2 1 1 RAW8 4096 1950 2 4500
2 4 1 RAW8 4096 2000 2 4650
2 1 4 RAW8 4096 2950 8 6200
2 4 4 RAW8 4096 3100 8 6800
4 1 1 RAW8 4096 2500 2 5550
4 4 1 RAW8 4096 2500 2 5750
4 1 4 RAW8 4096 3450 8 7250
4 4 4 RAW8 4096 3600 8 7750
8 1 1 RAW8 4096 3800 2 7650
8 4 1 RAW8 4096 3800 2 7900
8 1 4 RAW8 4096 4800 8 9300
8 4 4 RAW8 4096 4900 8 9900
1 4 1 RAW10 4096 2050 3 4900
2 4 1 RAW10 4096 2200 3 5100
4 4 1 RAW10 4096 2750 3 6450
8 4 1 RAW10 4096 4300 3 9050
1 4 1 RGB888 4096 2100 5 5100
2 4 1 RGB888 4096 2150 5 5300
4 4 1 RGB888 4096 2750 5 6550
8 4 1 RGB888 4096 4150 5 9100
1 — 1 Passthrough — 1400 2 3300
2 — 1 Passthrough — 1450 2 3500
4 — 1 Passthrough — 1950 4 4550
8 — 1 Passthrough — 3200 8 6750
Table 4.  CSI-2 Transmitter Performanceand Resource UtilizationThe following table shows the typical device resource utilization for selected configurations using the Quartus® Prime Pro Edition software version 24.1. The number of ALMs and logic registers are rounded up to the nearest 50. The number stated for M20K memory blocks includes no rounding.
Configuration ALMs M20K Memory Blocks Logic Registers
Data Lanes PPI Bus Width Pixel-in-Parallel Buffer Depth Data Type Supported
1 1 1 RAW8 4096 1550 7 3250
1 4 1 RAW8 4096 1600 7 3300
1 1 4 RAW8 4096 3050 10 5600
1 4 4 RAW8 4096 3100 10 5750
2 1 1 RAW8 4096 1550 7 3250
2 4 1 RAW8 4096 1600 7 3250
2 1 4 RAW8 4096 3000 10 5550
2 4 4 RAW8 4096 3100 10 5700
4 1 1 RAW8 4096 2000 6 3900
4 4 1 RAW8 4096 2000 6 3900
4 1 4 RAW8 4096 3450 9 6250
4 4 4 RAW8 4096 3550 9 6350
8 1 1 RAW8 4096 3250 10 5250
8 4 1 RAW8 4096 3250 10 5250
8 1 4 RAW8 4096 4700 13 7600
8 4 4 RAW8 4096 4800 13 7700
1 4 1 RAW10 4096 1700 8 3550
2 4 1 RAW10 4096 1700 8 3500
4 4 1 RAW10 4096 2200 7 4450
8 4 1 RAW10 4096 3700 11 6350
1 4 1 RGB888 4096 1700 9 3500
2 4 1 RGB888 4096 1700 9 3450
4 4 1 RGB888 4096 2150 8 4200
8 4 1 RGB888 4096 3500 12 5800
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