MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 4/26/2024
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Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interface Overview 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resource Utilization 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interface Overview x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PHY Protocol Interface (PPI) Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Streaming Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PHY-Protocol Interface (PPI) Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for Intel® FPGA IP Cores and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PHY Protocol Interface (PPI) Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interface Overview
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

3. MIPI CSI-2 Intel® FPGA IP Parameters

Table 17.  IP Core Parameters
Parameter Value Description
Direction RX, TX Select the port direction.
Video Interface Mode Video, Passthrough Select Video to decode RX video to/TX video from AXI4-Stream Video interface. Select Passthrough to interface using MIPI CSI-2 packets and disable packet encode/decode.
Buffer depth

128, 256, 512, 1024,

2048, 4096, 8192, 16384

 Select the FIFO buffer depth. For the Receiver, this is in units of pixels. For the Transmitter, this value is in bytes. In both cases, a recommended minimum value would contain 2 video lines, though this may need to be higher depending on the back-pressure characteristics of the user’s system.
Enable Scrambler/Descrambler True, False Enable CSI-2 scrambling on TX or CSI-2 descrambling on RX.
Number of lanes

1C & 1D, 1C & 2D,

1C & 4D, 1C & 8D

 Select the number of D-PHY lanes. C indicates clock lane while D indicates Data lane count.
PPI bus width per lane 16 Select the PHY Protocol Interface (PPI) bus width bits per lane.
Pixels in parallel 1, 2, 4 Select the number of pixels in parallel at the video streaming interface.
Number of video streaming interfaces 1 – 4 Select the number of AXI-S video interfaces/CSI-2 virtual channels.
Support RAW6 True, False Turn on to support handling the RAW6 video data type.
Support RAW7 True, False Turn on to support handling the RAW7 video data type.
Support RAW8 True, False Turn on to support handling the RAW8 video data type.
Support RAW10 True, False Turn on to support handling the RAW10 video data type.
Support RAW12 True, False Turn on to support handling the RAW12 video data type.
Support RAW14 True, False Turn on to support handling the RAW14 video data type.
Support RAW16 True, False Turn on to support handling the RAW16 video data type.
Support RAW20 True, False Turn on to support handling the RAW20 video data type.
Support RAW24 True, False Turn on to support handling the RAW24 video data type.
Support YUV420 8-bit True, False Turn on to support handling YUV420 8-bit video data type (Receiver only).
Support YUV420 8-bit (legacy) True, False Turn on to support handling YUV420 8-bit legacy video data type (Receiver only).
Support YUV420 10-bit True, False Turn on to support handling YUV420 10-bit video data type (Receiver only).
Support YUV422 8-bit True, False Turn on to support handling YUV422 8-bit video data type (Receiver only).
Support YUV422 10-bit True, False Turn on to support handling YUV422 10-bit video data type (Receiver only).
Support YUV444 True, False Turn on to support handling the YUV444 video data type.
Support RGB444 True, False Turn on to support handling the RGB444 video data type.
Support RGB555 True, False Turn on to support handling the RGB555 video data type.
Support RGB565 True, False Turn on to support handling the RGB565 video data type.
Support RGB666 True, False Turn on to support handling the RGB666 video data type.
Support RGB888 True, False Turn on to support handling the RGB888 video data type.
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