MIPI CSI-2 Intel® FPGA IP User Guide

ID 813926
Date 4/26/2024
Public

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2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals

Table 9.   Avalon® Memory-Mapped Interface Control Interface Signals
Signal Width Direction Description
control_address 10 Input

The Avalon® memory-mapped interface agent port that provides access to internal control and status register. This interface is expected to operate at Nios V processor clock domain. Because messages can be large (more than 4 Bytes), the IP transfers the message in burst mode with full handshaking mechanism.

Write transfers always have a wait time of 0 cycle while read transfers have a wait time of 1 cycle. The addressing should be accessed as word addressing in the Platform Designer flow. For example, addressing of 4 in the Nios V software selects the address of 1 in the agent.

control_write 1 Input
control_byteenable 4 Input
control_writedata 32 Input
control_read 1 Input
control_readdata 32 Output
control_readdatavalid 1 Output
control_waitrequest 1 Output
control_irq 1 Output Active high interrupt signal.