1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the GTS System PLL Clocks IP
3. Functional Description x
3.1. Architecture 3.2. Dynamic Reconfiguration Flow 3.3. Clocking and Reset Sequence 3.4. Timing Constraints 3.5. Operation Speed Switching 3.6. USXGMII 3.7. Fmax Requirement
3.1. Architecture x
3.1.1. 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) 3.1.2. 10M/100M/1G/2.5G/5G/10G (USXGMII) 3.1.3. 1G/2.5G/10G MGBASE PCS only
3.2. Dynamic Reconfiguration Flow x
3.2.1. RTL Generation using Dynamic Reconfiguration IP
3.2.1. RTL Generation using Dynamic Reconfiguration IP x
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP 3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments 3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool 3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
3.3. Clocking and Reset Sequence x
3.3.1. Clocking 3.3.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration Controller Interface Signals
5.6. GMII Signals x
5.6.1. 1G/2.5G/10G MGBASE PCS Only PMA Interface
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Signals for Signal Tap
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments

  • Modify the QSF settings to create the DR groups for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP variant. You can assign the profile numbers across the IP and set the physical locations of the transceiver lanes using the following QSF settings. 
    • set_global_assignment -name IP_FILE <ip_variant.ip>

      Example: set_global_assignment -name IP_FILE mrphy_1g_2p5g.ip 

    • set_global_assignment -name SYSTEMVERILOG_FILE support_logic/mr_top/synth/<DR Group name>

      Example: set_global_assignment -name SYSTEMVERILOG_FILE support_logic/mr_top/synth/mr_top.sv

  • Use the following QSF setting to add an instance of the IP variant to the DR group: 
    • set_instance_assignment -name DR_IP_INSTANCE <MRPHY IP component name> -to <instance name> -section_id <DR Group name>

      Example: set_instance_assignment -name DR_IP_INSTANCE mrphy_1g_2p5g -to inst_mrphy_1g_2p5g -section_id mr_top

  • Assign a profile ID to the IP variant instance. This number is used to trigger the reconfiguration in the DR controller registers. Number <N> must start at 1. 
    • set_instance_assignment -name DR_GROUP_RECONFIG_ID <N> -to <instance name> -section_id <DR Group name>

      Example: set_instance_assignment -name DR_GROUP_RECONFIG_ID 1 -to inst_mrphy_1g_2p5g -section_id mr_top

  • Set the relative physical location of the transceiver serial pins of the 1G/2.5G/5G/10G Multirate Ethernet PHY IP variant instance in the DR group. Relative physical location <X> is always 0 for 1G/2.5G/5G/10G Multirate Ethernet PHY as it uses single lane. 
    • set_instance_assignment -name DR_IP_INSTANCE_RELATIVE_LOCATION <X> -to <instance name> -section_id <DR Group name>

      Example: set_instance_assignment -name DR_IP_INSTANCE_RELATIVE_LOCATION 0 -to inst_mrphy_1g_2p5g -section_id mr_top

  • The below QSF assignments specifies that this variant IP instance is part of combination N. Here the combination starts at 1 and combination N (which in this case 1) is the startup combination. 
    • set_instance_assignment -name DR_COMBINATION <N> -to <instance name> -section_id <DR Group name>

      Example: set_instance_assignment -name DR_COMBINATION 1 -to inst_mrphy_1g_2p5g -section_id mr_top 

    • set_global_assignment -name DR_GROUP_STARTUP_COMBINATION <N> -section_id <DR Group name>

      Example: set_global_assignment -name DR_GROUP_STARTUP_COMBINATION 1 -section_id mr_top

Note: The <instance name>, <MRPHY IP component name>, and <DR group name> are user defined.
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